Double coding processes for mask read only memory (ROM) devices

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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438278, H01L 218236

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active

058858733

ABSTRACT:
The present invention includes forming a thin oxide layer and a polysilicon layer on a substrate. A thin silicon nitride layer is then formed on the polysilicon layer. An etching is performed to etch back the silicon nitride layer and the polysilicon layer on a NMOS cell region. Next, a blanket ion implantation is carried out to form lightly doped drain regions. A coding oxide layer is formed on the NMOS cell region. Then, the silicon nitride layer is stripped. A second polysilicon layer is successively deposited over the substrate. The polysilicon layer, the gate oxide layer and the coding oxide layer are patterned to form the gate structures. A second ion implantation is used to implant ions to form LDD regions. Side wall spacers are then formed on the side walls of the gate structures. Next, a third ion implantation is then carried out to dope ions into the substrate thereby forming source and drain regions. A high temperature thermal anneal is performed to activate the dopant.

REFERENCES:
patent: 4233671 (1980-11-01), Gerzberg et al.
patent: 4898838 (1990-02-01), Morris et al.
patent: 5786252 (1998-07-01), Ludikhuize et al.

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