Doping technique for MOS devices

Details Doping technique for MOS devices Doping technique for MOS devices

1997-12-09

1999-04-20

Chaudhuri, Olik

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438302, 438438, 257344, 257409, H01L 21316

Patent

active

058952381

ABSTRACT:
A method for manufacturing a semiconductor device having impurity doped regions serving as source and drain and a semiconductor device obtained by the application of the same method are disclosed. In the method, a semiconductor substrate having a gate oxide is prepared, and a gate electrode is formed on the gate oxide. A first dielectric film is formed on the semiconductor substrate impurity ions of a first conductive type into the semiconductor substrate while permitting the gate electrode and the first dielectric film formed on the side walls of the gate electrode to serve as self-aligning masks. Then, a second dielectric film to be deposited on the first dielectric film, and an anisotropic etching is effected on at least on the second dielectric film to form on the side walls of the gate electrode spacers having a prescribed profile. Thereafter, impurity ions of a second conductive type are implanted into the semiconductor substrate while permitting the gate electrode and the spacers to serve as self-aligning masks.

REFERENCES:
patent: 5565700 (1996-10-01), Chou et al.
Sidewall Spacer Construction, IBM Technical Disclosure Bulletin, Oct. 1986, vol. 19, NR 5, pp. 2342-2343.
Self-Aligned Borderless Diffusion contacts, IBM Technical Disclosure Bulletin, Dec. 1988, vol. 31, NR 7, , pp. 242-243.

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