Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-04-26
2002-06-04
Weiss, Howard (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
Reexamination Certificate
active
06399434
ABSTRACT:
BACKGROUND OF THE INVENTION
In construction of microelectronic devices, it is well known that there is a constant pressure for reduction of device size and/or increase of device capability at a given scale.
In the actual construction of reduced scale devices, attention must be paid to higher precision in configuring the materials from which the device components are formed. A common configuration task is the positioning of dopant species within various semiconductor segments making up the ultimate device.
Control of the configuration (e.g., location and amount) of dopant species becomes especially important in the context of finer sized device components which are more sensitive to adverse dopant effects since the amount of material forming the component is smaller. For example, an interaction caused by dopant migration from one device component to another that might have only affected the border area of a large component would affect an entire component of smaller scale (e.g., where the scale of the smaller component is the same size as the border area of the larger component). Thus, reduction in component scale forces consideration of dopant configuration problems which could have been viewed as non-critical for larger scale components. Control of the dopant configuration must be considered during the device manufacture process, during device testing, and during device operation.
In the context of devices such as MOSFET transistors in semiconductor substrates, various materials are used to form the components of the transistor such as the source and drain diffusion regions, electrical contacts (studs) to the diffusion regions, various dielectric regions, gate conductor, gate oxide, etc. For example, the studs are typically metal (i.e. tungsten) or a highly doped polycrystalline silicon (polysilicon) material whereas the source and drain diffusion regions may be very shallow regions of more precise dopant level in the monocrystalline semiconductor substrate. The successful functioning of the transistor depends in part on the ability of these diverse materials to maintain their original or desirably modified character during manufacture/useful life of the device.
Unfortunately, the nature of these materials is such that unwanted dopant interactions may occur unless otherwise prevented. For example, ultra-shallow junctions (required for scalability of MOSFETs to channel lengths significantly shorter than 100 nm) present challenges to successfully forming contacts to source/drain diffusions.
In particular with ultra-shallow junctions, the contact metallurgy (the conductive stud) is prone to “spike through” to the junction edge, which results in excessive leakage currents. One technique which is commonly employed in the art avoids contact metallurgy “spike through” by forming a locally deep junction in the contact hole prior to the deposition of the conductive stud material. Additionally, in the absence of an additional deeper diffusion, crystal defects are likely to propagate from the interface between the contact metallurgy and the silicon substrate into the depletion region of the source-drain diffusion. These silicon defects also result in increased junction leakage currents. Although this deeper diffusion is spaced away from the gate conductor, its presence still degrades the short channel characteristics of the MOSFET since ultra-short channel MOSFETs are very sensitive to junction depth. Furthermore, because of alignment tolerance, the proximity of the deeper diffusion to the gate edge may vary randomly. This results in statistical variation of the electrical characteristics of the MOSFET. Therefore, the prior art technique used for contacting source-drain diffusions does not allow the MOSFET to be scaled in an optimal manner.
Additionally, the contact metallurgy may interact with the monocrystalline semiconductor substrate altering the doping of the diffusion in an undesirable manner. In the case of a tungsten stud, dopant may diffuse from the junction into the stud. This lowers the average doping concentration and increases the resistance of the diffusion. Increased diffusion resistance slows the switching speed of the MOSFET. For a polysilicon stud, which is customarily heavily doped to provide low resistance, dopant from the stud may diffuse into the semiconductor substrate. The out-diffusion from the stud may result in an excessively deep diffusion, which degrades the electrical characteristics (i.e. poorer threshold voltage control, increased off-state leakage current) of the MOSFET.
One approach to avoid unwanted interaction has been to employ a thick intrinsically conductive compound barrier (e.g. TiN or silicide) between the stud and the shallow source/drain diffusion region. See for example, the discussion in “Fundamentals of Semiconductor Processing Technologies” by B. El-Kareh, Kluwer Academic Publishers, (1995), p. 534-546. These modifications may introduce other materials interaction problems and/or add significantly to the cost/complexity of the fabrication process.
U.S. pat. application Ser. No. 09/295,132, filed Apr. 20, 1999, discloses use of quantum conductive barriers at shallow junctions to address dopant interaction problems. Nevertheless, there is a need for improved barrier materials and structures that provide improved control over dopant atoms commonly present in semiconductor electronic devices.
SUMMARY OF THE INVENTION
The invention provides novel and improved barrier layer structures and compositions which enable reduced scale device structures. The barriers of the invention advantageously enable the control of dopant diffusion profile for a given thermal history and dopant configuration.
In one aspect, the invention encompasses a semiconductor structure comprising at least two distinct semiconductor regions, each region having a common dopant species and a thin interface layer between the regions and contacting the regions, the interface layer comprising silicon, nitrogen, and oxygen atoms and having a thickness of about 5 to 50 Å. The barrier layer compositions enable control (in combination with the thermal history of the subject device) of dopant concentration and depth profile.
In another aspect, the invention encompasses a method of forming a doped semiconductor structure, the method comprising:
(a) providing a first semiconductor material region,
(b) forming an interface layer comprising silicon, oxygen, and nitrogen on the first region,
(c) forming a second semiconductor material region on the interface layer, the second semiconductor material region being on an opposite side of the interface layer from the first semiconductor material region,
(d) providing a dopant in the second region, and
(e) heating the first and second regions whereby at least a portion of the dopant diffuses from the second region through the interface layer to the first region.
These and other aspects of the invention are described in further detail below.
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Chaloux Susan E.
Faltermeier Johnathan E.
Gruening Ulrike
Jammy Rajarao
Parks Christopher C.
Capella Steven
Trinh (Vikki) Hoa B.
Weiss Howard
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