Doped polysilicon to retard boron diffusion into and through thi

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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438306, 438528, 438585, H01L 21336

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active

060308745

ABSTRACT:
An embodiment of the instant invention is a method of fabricating a semiconductor device which includes a dielectric layer situated between a conductive structure and a semiconductor substrate, the method comprising the steps of: forming the dielectric layer (layer 14) on the semiconductor substrate (substrate 12); forming the conductive structure (structure 18) on the dielectric layer; doping the conductive structure with boron; and doping the conductive structure with a dopant which inhibits the diffusion of boron. The semiconductor device may be a PMOS transistor or a capacitor. Preferably, the conductive structure is a gate structure. The dielectric layer is, preferably, comprised of a material selected from the group consisting of: an oxide, an oxide/oxide stack, an oxide
itride stack, and an oxynitride. Preferably, the dopant which inhibits the diffusion of boron comprises at least one group III or group IV element. More specifically, it is preferably comprised of: carbon, germanium, and any combination thereof. Preferably, the steps of doping the conductive structure with boron and doping the conductive structure with a dopant which inhibits the diffusion of boron are accomplished substantially simultaneously, or the step of doping the conductive structure with boron is preformed prior to the step of doping the conductive structure with a dopant which inhibits the diffusion of boron are accomplished substantially simultaneously.

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Nakayama, Satoshi, A P+ poly-Si gate with nitrogen-doped poly-Si layer for deep submicron PMOSFEts, NTT LSI Laboratories, Abstract No. 301., p. 445-446.
Okazaki, et al., Characteristics of Sub-1/4-.mu.m Gate Surface Channel PMOSFET's Using a Multilayer Gate Structure of Boron-Doped Poly-Si on Thin Nitrogen-Doped Poly-Si, 1994 IEEE, p. 2369-2375.
Okazaki, et al., Sub-1/4-.mu.m Dual-Gate CMOS Technology Using In-Situ Doped Polysilicon for nMOS and pMOS Gates, IEEE Transactions on Electron Devices, vol. 42, No. 9, Sep. 1995, p. 1583-1589.
Grider, et al., Ultra-Shallow Raised p+-n Junctions Formed by Diffusion from Selectively Deposited In-Situ Doped Si.sub.0.7 Ge.sub.0.3, Journal of Electronic Materials, vol. 24, No. 10, 1995, p. 1369-1376.

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