Dopant profile tuning for MOS devices by adapting a spacer...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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Details

C438S303000, C438S306000, C257SE21640, C257SE21626, C257SE21634, C257SE21619

Reexamination Certificate

active

07977179

ABSTRACT:
By selectively modifying the spacer width, for instance, by reducing the spacer width on the basis of implantation masks, an individual adaptation of dopant profiles may be achieved without unduly contributing to the overall process complexity. For example, in sophisticated integrated circuits, the performance of transistors of the same or different conductivity type may be individually adjusted by providing different sidewall spacer widths on the basis of an appropriate masking regime.

REFERENCES:
patent: 6479350 (2002-11-01), Ling et al.
patent: 6696334 (2004-02-01), Hellig et al.
patent: 6806584 (2004-10-01), Fung et al.
patent: 7727870 (2010-06-01), Zhang et al.
patent: 2005/0190421 (2005-09-01), Chen et al.
patent: 2006/0118878 (2006-06-01), Huang et al.
patent: 2006/0151776 (2006-07-01), Hatada et al.
patent: 2007/0020866 (2007-01-01), Cheng
Correspondence from foreign associate dated Jul. 21, 2008.

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