Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
1998-10-22
2002-04-30
Ghyka, Alexander G. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S560000, C438S592000
Reexamination Certificate
active
06380055
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is related to the manufacture of insulated gate field effect transistors, and more particularly to the structure and doping of gate electrode structures therein.
2. Description of the Related Art
An insulated-gate field-effect transistor (IGFET), such as a metal-oxide semiconductor field-effect transistor (MOSFET), uses a gate electrode to control an underlying surface channel joining a source and a drain. The channel, drain and source are located in a semiconductor substrate, with the channel being doped oppositely to the drain and source. The gate electrode is separated from the semiconductor substrate by a thin insulating layer (i.e., a gate dielectric layer) such as an oxide. The operation of the IGFET involves application of an input voltage to the gate electrode, which sets up a transverse electric field in the channel in order to modulate the longitudinal conductance of the channel.
In typical IGFET processing, the source and drain are formed by introducing dopants of a second conductivity type (P or N) into the semiconductor substrate of a first conductivity type (N or P) using a patterned gate electrode as a mask. This self-aligning procedure tends to improve packing density and reduce parasitic overlap capacitances between the gate electrode and the source/drain regions. Polysilicon (also called polycrystalline silicon, poly-Si, or just “poly”) thin films are typically used as the gate electrode. Since polysilicon has the same high melting point as a silicon substrate, it can be deposited prior to source and drain formation. The polysilicon is anisotropically etched through openings in a photoresist mask to provide a gate electrode which forms a mask during formation of the source and drain by ion implantation. Photolithography is used to create patterns in the photoresist mask that define the gate electrode.
The gate electrode is typically doped by the same type of ion implantation as are the source and drain. For example, boron is frequently implanted to form the source and drain in a P-channel IGFET, and the boron is also implanted into the gate electrode of the IGFET to create a P-type polysilicon gate electrode. However, because boron is such a “light” atom (i.e., low atomic mass), boron implanted into the polysilicon gate electrode can easily diffuse along the grain boundaries of the polysilicon and into the gate oxide, and may diffuse ultimately into the underlying channel region. The presence of boron in the channel affects the device parameters of the IGFET, especially the threshold voltage, and the presence of boron in the gate oxide can affect the reliability of the IGFET. Both effects are tremendously undesirable.
A number of techniques have been utilized to reduce diffusion of dopants, especially boron, into the gate dielectric and into the underlying channel. One such method is disclosed by Fang, et al, in a paper entitled “Low-Temperature Furnace-Grown Reoxidized Nitrided Oxide Gate Dielectrics as a Barrier to Boron Penetration,”
IEEE Electron Device Letters,
Vol. 13, No. 4, April, 1992, which includes a nitridation of a partially grown gate oxide, followed by an additional oxidation step. Polysilicon is then deposited on the reoxidized nitrided oxide and etched to form gate electrodes.
Other similar methods are disclosed by Joshi, et al in a paper entitled “Oxynitride Gate Dielectrics for P+-polysilicon Gate MOS Devices,”
IEEE Electron Device Letters,
Vol. 14, No. 12, December, 1993, which compares several similar methods of forming oxynitride gate dielectrics.
While such methods are helpful in reducing boron penetration into the channel, the desired gate oxide thickness continues to decrease. The effectiveness of earlier techniques may diminish with decreasing gate oxide thickness. Accordingly, there is a need for improved techniques for reducing dopant penetration (especially boron) into the gate oxide and into the channel region.
SUMMARY OF THE INVENTION
The present invention improves upon the previous techniques for retarding dopant diffusion into the gate dielectric by incorporating a diffusion barrier region within a layer of polysilicon. The barrier region is a nitrogen-containing, diffusion-retarding barrier region. The portion of the polysilicon layer above the barrier region is doped more heavily than the portion below, and the barrier region serves to keep most of the dopant within the upper portion. The barrier region nevertheless allows some of the dopant to diff-use into the lower portion, which ensures that the polysilicon layer forms a gate electrode which is a single contiguous electrical node rather than an insulating portion due to polysilicon depletion effects.
The barrier region is formed by implanting a nitrogen-containing material, such as elemental nitrogen or molecular nitrogen, so that a region is formed within the polysilicon layer. The thickness of the nitrogen-containing region may be chosen for its ability to conduct current therethrough while retaining its ability to retard dopant diffusion, and may be chosen to be approximately 5-15 Å thick.
By use of this invention, any nitrogen residing at the top of the gate dielectric may be kept to a concentration less than approximately 2%. The dopant concentration at the first polysilicon layer bottom surface may exceed approximately 1×10
21
atoms/cm
3
. The present invention is particularly well suited to thin gate dielectrics, such as a those having a thickness less than approximately 60 Å when using a p-type dopant, such as B, BF
2
, and other similar compounds of boron and flourine (e.g., BF
x
).
In one embodiment for a semiconductor manufacturing process, a method of fabricating a gate electrode structure for an insulated gate field effect transistor includes the steps of: (1) forming a polysilicon layer on an underlying gate dielectric layer, the polysilicon layer having top and bottom surfaces, the bottom surface forming an interface with said gate dielectric layer; (2) implanting a nitrogen-containing material to form a nitrogen-containing diffusion-retarding barrier region within the polysilicon layer; (3) introducing a dopant into at least a portion of the polysilicon layer disposed between the barrier region and the top surface, resulting in a greater dopant concentration immediately above the barrier region than immediately below; and (4) removing regions of the polysilicon layer to form a gate electrode for the IGFET.
In another embodiment, the method includes the additional step of implanting a nitrogen-containing material to form a second nitrogen-containing diffusion-retarding barrier region above and spaced apart from the first nitrogen-containing diffusion-retarding barrier region.
In yet another embodiment of the present invention, a semiconductor gate electrode structure for an insulated gate field effect transistor includes: (1) a polysilicon layer formed on an underlying gate dielectric layer, the polysilicon layer having respective top and bottom surfaces, the bottom surface forming an interface with said gate dielectric layer; (2) a first nitrogen-containing diffusion-retarding barrier region formed within the polysilicon layer; and (3) a dopant within the polysilicon layer having a greater dopant concentration immediately above the diffusion barrier region than immediately below.
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Dawson Robert
Fulford Jr. H. Jim
Gardner Mark I.
Hause Frederick N.
Michael Mark W.
Advanced Micro Devices , Inc.
Ghyka Alexander G.
Skjerven Morrill & MacPherson LLP
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