Domino scan architecture and domino scan flip-flop for the testi

Details Domino scan architecture and domino scan flip-flop for the testi Domino scan architecture and domino scan flip-flop for the testi

1996-05-29

1999-02-02

Santamauro, Jon

Electronic digital logic circuitry

With test facilitating feature

326 93, 326 98, 371 221, H03K 1996, H03K 1900, G01R 3128

Patent

active

058670360

ABSTRACT:
Hybrid CMOS circuit configurations that include both static CMOS logic and Domino CMOS logic include two registers that surround the Domino logic to allow that logic to be tested. One register receives an input test vector, loaded directly through a primary set of inputs or by a serial scan chain if the register inputs are not directly accessible. The second register latches the results of the test vector application. The register contents can either be read directly through a primary set of outputs if there is no static CMOS logic between the register outputs and a primary set of circuit outputs, or scanned out of the second register using a serial scan chain. Domino scan flip-flops, which reduce transistor count over conventional static scan flip-flops, can be used in the Domino logic as sequential elements to implement multiple logic functions. These scan flip-flops can be serially connected as part of a separate scan chain or integrated into a single scan chain with the registers and any other static scan flip-flops in the circuit. Domino scan flip-flops allow all of the nominal logic to be tested in conjunction with the two registers. A Domino clock used to drive the Domino logic and a system clock used to drive the static CMOS logic ensures that correct test data is applied and read out from the hybrid circuit.

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