Domain crossing device

Details Domain crossing device Domain crossing device

2008-03-04

2008-03-04

Butler, Dennis M. (Department: 2115)

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

Using delay

C713S500000, C713S503000

Reexamination Certificate

active

07340632

ABSTRACT:
A domain crossing device for use in a semiconductor memory device, including: a unit for comparing a phase of an internal clock signal with a phase of a delay locked loop (DLL) clock signal to generate a first clock selection signal and a phase detection period signal in response to a detection starting signal and a second clock selection signal; a unit for generating a plurality of initial latency signals in response to the phase detection period signal, the detection starting signal and a column address strobe (CAS) latency signal; a unit for receiving the plurality of initial latency signals and the detection starting signal to generate a plurality of latency signals, a clock selection signal and the second clock selection signal; and a unit for generating the detection starting signal based on a self refresh signal, a power-up signal and a DLL disable signal.

REFERENCES:
patent: 6980479 (2005-12-01), Park
patent: 2002/0129215 (2002-09-01), Yoo et al.
patent: 2003/0081713 (2003-05-01), Pontius et al.
patent: 2004/0105292 (2004-06-01), Matsui
patent: 2004/0107373 (2004-06-01), Ferrara
patent: 2004/0218461 (2004-11-01), Park
patent: 2004-327008 (2004-11-01), None

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