DMOS transistor protected against "snap-back"

Details DMOS transistor protected against "snap-back" DMOS transistor protected against "snap-back"

1997-11-07

2000-03-28

Clark, Sheila V.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257342, H01L 2976

Patent

active

060435321

ABSTRACT:
The DMOS transistor includes an n drain region, a p body region which forms, with the drain region, a junction having at least one edge portion with a small radius of curvature, an n+ source region which delimits a channel in the body region, p+ body contact regions, a gate electrode, a source and body electrode, and a drain electrode. To prevent the "snap-back" phenomenon when the junction is reverse biased with the source, body and gate electrodes short-circuited, a p+ region is associated with each of the edge portions having a small radius of curvature and is arranged so as to be closer to the associated edge portion than any part of the source region.

REFERENCES:
patent: 4831423 (1989-05-01), Shannon
patent: 5182222 (1993-01-01), Malhi et al.

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