Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-08-17
2001-06-26
Lee, Eddie C. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S335000, C257S338000, C257S339000, C257S368000, C257S369000, C257S371000
Reexamination Certificate
active
06252279
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a power semiconductor device and, more particularly, to a double diffused MOS field effect (DMOS) transistor having high reliability and a method for fabricating the same.
2. Description of the Related Art
A conventional MOS field effect transistor (MOSFET) has the following advantages compared to a bipolar transistor when both are used for power devices. First, the power MOSFET has a high input impedance providing a high power gain using a simple gate driving circuit. Second, the power MOSFET is a unipolar device preventing the time delay caused by the accumulation or recombination of minority carriers while the device is turned off. Accordingly, the use of the power MOSFET for a switching mode power supply, a lamp ballast, and a motor driving circuit has grown.
A DMOS transistor using a planar diffusion technique is typically used as the power MOSFET.
FIG. 1
is a cross-sectional view of a conventional DMOS transistor. Referring to
FIG. 1
, an N-type well
4
having a single concentration is formed on a P-type semiconductor substrate
2
. A drain
6
doped with a high concentration of N-type impurities is formed in the N-type well
4
. A P-type body region
8
is formed in the semiconductor substrate
2
spaced at a predetermined distance from the N-type well
4
. A P
+
impurity region
10
for controlling the bias of the body region and a source
12
doped with a high concentration of N-type impurities are formed adjacent each other within the body region
8
.
A field insulative film
14
for providing isolation between devices is formed on the semiconductor substrate
2
. A gate electrode
18
is formed on the semiconductor substrate
2
. A gate insulative film
16
is formed between the gate electrode
18
and the semiconductor substrate
2
. An interlayer insulative film
20
for insulating the transistor from other conductive layer is formed on the resultant stricture. A drain electrode
22
coupled to the drain
6
and a source electrode
24
coupled to the source
12
and the P
+
impurity region
10
are formed through contact holes formed in the interlayer insulative film
20
.
According to the conventional DMOS, since the N well
4
has a single concentration profile, an electric field crowds at the edges of the drain
6
or gate electrode
18
on the semiconductor substrate when a high voltage is applied to the drain
6
causing breakdown to occur even at a low voltages. Also, because of the segregation of ion-implanted impurities into the N well
4
when the field oxide film
14
is formed, the impurity concentration at the lower portion of the field oxide film
14
is higher than that of a bulk region. Thus, an electric field crowds at the lower portion of the field oxide film
14
causing breakdown to occur when the DMOS is not completely depleted.
To counteract this phenomenon, the conventional DMOS transistor shown in
FIG. 2
has been proposed. The same reference numerals denote the same members or regions in
FIGS. 1-3
. Referring to
FIG. 2
, a P-type impurity region
26
is formed in the N well
4
under the field oxide film
14
. Doing so, provides a high breakdown voltage by preventing a high concentration of impurities at the lower portion of the field oxide film
14
due to segregation of impurities during the forming of the field oxide film
14
. However, the current characteristics are considerably degraded compared to the DMOS of FIG.
1
.
FIG. 3
is a cross-sectional view of still another conventional DMOS transistor. The DMOS transistor shown prevents breakdown in the structures of
FIGS. 1 and 2
caused by electric field concentration at the edges of a drain electrode. Referring to
FIG. 3
, a polysilicon field plate
28
is formed on the field oxide film
14
corresponding to the edges of the drain
6
. The field plate
28
prevents concentration of the electric field at the edges of the drain electrode
22
of
FIG. 1
allowing a higher breakdown voltage to be maintained.
The above-described conventional DMOS transistors have large base resistance and large pinch resistance. Because of this, it is difficult to prevent the operation of a parasitic NPN bipolar transistor. Also, breakdown occurs on the surface rather than the bulk of a semiconductor substrate degrading the reliability of the device and requiring an additional device for counteracting the reliability degradation.
Accordingly, a need remains for a DMOS transistor having a high reliability.
SUMMARY OF THE INVENTION
It is an object of the present invention to overcome the problems associated with conventional DMOS transistors.
It is another object of the present invention to provide a DMOS transistor that improves the breakdown voltage characteristics of a device.
It is yet another object of the present invention to provide a DMOS transistor that improves the reliability of the device by preventing breakdown near the surface of the semiconductor substrate.
It is still another object of the present invention to provide a method for fabricating the DMOS transistor.
Accordingly, a DMOS transistor is provided. The DMOS transistor of the present invention comprises a semiconductor substrate having a first conductivity type. A semiconductor region having a second conductivity type is formed on the semiconductor substrate. A drain having the second conductivity type is formed on the semiconductor region. A high concentration buried impurity layer having the second conductivity type is formed on the semiconductor region under the drain. A body region having the first conductivity type is formed on the semiconductor substrate spaced a predetermined distance from the semiconductor region. A source having the second conductivity type formed on the body region. A gate electrode is formed on the semiconductor substrate having a gate insulative film formed thereon. Source and drain electrodes are coupled respectively to the source and the drain.
The DMOS transistor further comprises a sink region having the second conductivity type coupling the drain to the high concentration buried impurity layer. The second conductivity type may be an N type and the drain, the high concentration buried impurity layer, and the sink region have impurity concentrations with a relation of N
++
>N
+
>N
0
, respectively.
The power DMOS transistor may include a low concentration buried impurity layer formed below the drain, the low concentration buried impurity layer surrounding the high concentration buried impurity layer. The semiconductor region may also include an epitaxial layer having the second conductivity type. The semiconductor region may comprise a well region having the second conductivity type and an epitaxial layer having the second conductivity type formed on the well region.
The DMOS transistor further comprises a high concentration first impurity region having the first conductivity type formed below the body region and contacting the body region. A field oxide film is formed on the semiconductor region between the drain and the source and a second impurity region having the first conductivity type formed under the field oxide film for improving the breakdown voltage characteristics of the transistor. A third impurity region having the second conductivity type is formed in the body region adjacent to the source, the third impurity region having a higher concentration of impurities than the body region. A conductivity film pattern is formed on the field oxide film at both sides of the drain, the conductivity film pattern serving as a field plate for preventing concentration of an electric field at edges of the drain.
Another embodiment of the DMOS transistor of the present invention comprises a semiconductor substrate having a first conductivity type. A semiconductor region having a second conductivity type is formed on the semiconductor substrate. A drain having the second conductivity type is formed on the semiconductor region. A body region having the first conductivity type is fo
Lee Eddie C.
Marger Johnson & McCollomm, P.C.
Ortiz Edgardo
Samsung Electronics Co,. Ltd.
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