DMA descriptor queue read and cache write pointer arrangement

Details DMA descriptor queue read and cache write pointer arrangement DMA descriptor queue read and cache write pointer arrangement

2005-06-17

2009-02-24

Chen, Alan (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output data buffering

C710S022000, C711S100000

Reexamination Certificate

active

07496699

ABSTRACT:
Method and apparatus for retrieving buffer descriptors from a host memory for use by a peripheral device. In an embodiment, a peripheral device such as a NIC includes a plurality of buffer descriptor caches each corresponding to a respective one of a plurality of host memory descriptor queues, and a plurality of queue descriptors each corresponding to a respective one of the host memory descriptor queues. Each of the queue descriptors includes a host memory read address pointer for the corresponding descriptor queue, and this same read pointer is used to derive algorithmically the descriptor cache write addresses at which to write buffer descriptors retrieved from the corresponding host memory descriptor queue.

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