DLL phase detection using advanced phase equalization

Details DLL phase detection using advanced phase equalization DLL phase detection using advanced phase equalization

2004-05-18

2008-09-02

Perveen, Rehana (Department: 2116)

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

Using delay

C713S400000, C713S500000, C713S501000, C713S502000, C713S503000, C713S600000, C713S601000, C327S141000, C327S163000

Reexamination Certificate

active

07421606

ABSTRACT:
A system and method are disclosed to generate and terminate clock shift modes during initialization of a synchronous circuit (e.g., a delay-locked loop or DLL). Upon initialization, the DLL is entered into a ForceSL (Force Shift Left) mode and an On1xmode (i.e., left shifting on each clock cycle). The feedback clock that tracks the phase of the reference clock (which, in turn, is derived from the system clock) is initially delayed in a coarse phase detector prior to applying it to the coarse phase detection window. Two delayed versions of the feedback clock are sampled by the reference clock to generate a pair of phase information signals, which are then used to establish an advanced phase equal (APHEQ) signal. The APHEQ signal advances onset of the PHEQ (phase equalization) phase and is used to terminate the ForceSL and On1xmodes, thereby preventing wrong ForceSL exit due to clock jitter or feedback path overshooting during On1xexit. The avoidance of wrong ForceSL exit and On1xovershooting problems further results in faster DLL locking time.

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Article titled “DDR SDRAM Functionality and Controller Read Data Capture” available at http://download.micron.com/pdf/pubs/designline/dl399.pdf, on Mar. 15, 2004, 24 pgs.

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