Divided-bit line type dynamic semiconductor memory with main and

Details Divided-bit line type dynamic semiconductor memory with main and Divided-bit line type dynamic semiconductor memory with main and

1987-08-26

1988-10-11

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365227, 365230, G11C 1140

Patent

active

047776250

ABSTRACT:
There is disclosed a divided-bit line type dynamic random access memory having parallel main bit line pairs which are formed on a substrate and to each of which sub-bit line pairs are provided in parallel with each other. Parallel word lines insulatively cross the sub-bit line pairs. Memory cells are provided at the crossing points of the sub-bit line pairs and the word lines. Each memory cell has a capacitor for storing information and a voltage-controlled switching transistor such as a MOSFET. First sense amplifier circuits are connected to the sub-bit line pairs, while second sense amplifier circuits are connected to the main bit line pairs. In a restoring mode, a specific sub-bit line pair, to which a selected memory cell is connected, is electrically disconnected from the corresponding main bit one pair, and a first sense amplifier circuit connected thereto is activated to perform a restoring operation. At this time, the remaining sub-bit line pairs other than the specific sub-bit line pair are also connected to the corresponding main bit line pair, and the first sense amplifier circuits of the remaining sub-bit line pairs are rendered inoperative to save power consumption.

REFERENCES:
patent: 4421996 (1983-12-01), Chuang et al.
patent: 4616342 (1986-10-01), Miyamoto
patent: 4628486 (1986-12-01), Sakui
IEEE International Solid-State Circuits Conference, "A 4Mb DRAM with Cross-point Trench Transistor Cell", Chattergee et al, Feb. 1986, pp. 268-269.

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