Divided bit line type dynamic random access memory with charging

Details Divided bit line type dynamic random access memory with charging Divided bit line type dynamic random access memory with charging

1988-11-23

1990-05-15

Moffitt, James W.

Static information storage and retrieval

Read/write circuit

Precharge

365149, 36518901, 365205, 365208, 365210, G11C 700, G11C 1124

Patent

active

049263820

ABSTRACT:
A divided bit line type dynamic semiconductor memory device comprises parallel main bit line pairs, divided bit line pairs provided at each main bit line pair, parallel word lines insulatively crossing the divided bit line pairs, and memory cells provided at the cross points between the divided bit line pairs and the word lines. First sense amplifiers are coupled to the divided bit line pairs. Second sense amplifiers are coupled to the main bit line pairs. First transfer gate sections are coupled between the divided bit line pairs and the main bit line pairs, respectively. Second transfer gate sections are coupled between the main bit line pairs and the second sense amplifier circuits, respectively. A charging/discharging current suppressor is provided which, in both of the read and restoring modes, restricts the amplitude of the potential change, due to charging/discharging, of a specifi main bit line pair associated with a selected divided bit line pair including a selected cell to be smaller than a full potential change defined by the source voltage and ground potential of the device, whereby a charging/discharging cuffent flowing through the specific main bit line pair is reduced so that the dissipation power of the dRAM is saved and its operation speed is improved.

REFERENCES:
patent: 4748591 (1988-05-01), Itoh et al.
patent: 4777625 (1988-10-01), Sakui et al.

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