Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-06-13
2004-01-06
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S718000
Reexamination Certificate
active
06675336
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method and/or architecture for distributed testing of circuitry generally and, more particularly, to a method and/or architecture for a distributed memory built in self test for multiport RAMs.
BACKGROUND OF THE INVENTION
Conventional multiport RAMs require complex circuitry. The complex circuitry makes determining whether a circuit is defective and/or where the defect is located both difficult and time consuming. Conventional built in self-test (BIST) circuits reduce the time and effort required for determining defects, since the BIST circuits can run self tests. The results from the self test can be analyzed to determine if the circuit is causing a problem and, if so, where the problem might be occurring in the circuit. Conventional BIST circuits, due to standard interfaces and centralized circuitry, are suited for board level BIST code generation. Conventional BIST circuits have limited interfacing capabilities. Additionally, conventional BIST circuits are not implemented to generate BIST code for embedded memories.
Furthermore, conventional BIST circuits impact RAM access and maximum frequency of operation of memory BIST (MBIST) circuits. The MBIST circuits require complex circuit routing and have limited interface capabilities due to area constraints. Conventional BIST circuits implement a centralized MBIST control block, a centralized address generator and a centralized data generator. The centralized components require complex routing. Additionally, layout versus schematic verification for MBIST circuits can be difficult.
SUMMARY OF THE INVENTION
The present invention concerns an apparatus comprising a first circuit and a second circuit. The first circuit generally comprises a first built in self test (BIST) circuit configured to test the first circuit. The second circuit generally comprises a second BIST circuit configured to test the second circuit. The second circuit may not be adjacent to the first circuit.
The objects, features and advantages of the present invention include providing a method and/or architecture for implementing a built in self test circuit that may (i) be implemented in embedded memories, (ii) run a memory test without impacting RAM access time, (iii) require minimal circuit routing, (iv) reduce circuit complexity and size, (v) allow implementation of local BIST address generation logic, (vi) allow implementation of local BIST data generation logic, and/or (vii) allow implementation of local BIST comparator logic.
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Hamadeh Emad
Narayana Pidugu L.
Thakur Sangeeta
Christopher P. Maiorana P.C.
Cypress Semiconductor Corp.
De'cady Albert
Torres Joseph D.
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