Disk array device with utilization of a dual-bus...

Details Disk array device with utilization of a dual-bus... Disk array device with utilization of a dual-bus...

2006-02-21

2006-02-21

Kim, Hong Chong (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Shared memory area

C711S130000, C710S033000, C710S040000, C710S107000, C710S307000

Reexamination Certificate

active

07003637

ABSTRACT:
In a disk control device arranged to include a CPU, a plurality of channel control units, a plurality of disk control units, a cache memory, and a data transfer integrated circuit communicably connected to the cache memory via a plurality of data buses, when receiving a request for access to the cache memory from any one of the CPU, the channel control units and the disk control units, the data transfer integrated circuit provides access to the cache memory by use of a certain number of one or ones of the data buses, which number is determinable in accordance with a transfer data length that is set in the access request.

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