Directory memory system having simultaneous write and comparison

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch

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365230, 364200, G11C 700

Patent

active

046163417

ABSTRACT:
A directory memory system having simultaneous writing and bypass capabilities. A data output bit from a respective memory cell of a memory array is applied to a control input of a first differential amplifier, while comparison input data is applied to inputs of a second differential amplifier. The outputs of corresponding transistors of the two differential amplifiers are connected together. Current switch transistors, operated in response to a bypass select signal, supply current only to one or the other of the two differential amplifiers. The differential output signal produced across the commonly connected outputs of the two differential amplifier circuits is buffered and amplified with a push-pull output circuit.

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Dussault et al, "Read Write Scheme for Bipolar Random-Access Memories Using Schottky Coupled Cells", IBM Tech. Disc. Bull., vol. 24, No. 11A, Apr. '82, pp. 5632-5633.

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