Direct tunneling semiconductor memory device and fabrication...

Details Direct tunneling semiconductor memory device and fabrication... Direct tunneling semiconductor memory device and fabrication...

2007-09-14

2008-10-07

Prenty, Mark (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S264000

Reexamination Certificate

active

07432153

ABSTRACT:
A direct-tunneling semiconductor memory device includes a device isolation structure formed on a semiconductor substrate, including a device isolation trench and a device isolation insulation film filling the device isolation trench, a dielectric film covering both sidewall surfaces and a top surface of a floating gate electrode formed on the semiconductor substrate, a conductive part provided on the sidewall surfaces of the floating gate electrode via the dielectric film, the conductor part constituting a part of a control gate electrode, and first and second diffusion regions formed at respective lateral sides of the floating gate electrode, wherein the first and second diffusion regions are formed on a surface of the device isolation groove with offset from a region right underneath the floating gate electrode, the conductive part is formed in the device region with offset from the device isolation trench.

REFERENCES:
patent: 6195292 (2001-02-01), Usuki et al.
patent: 6713826 (2004-03-01), Uehara et al.
patent: 7288813 (2007-10-01), Tsunoda et al.
patent: 11-103052 (1999-04-01), None
patent: 2000-150680 (2000-05-01), None
patent: 2002-016155 (2002-01-01), None
patent: 2002-231824 (2002-08-01), None
patent: 2004-273643 (2004-09-01), None
Tatsuya Usuki et al., “Advantage of a Quasi-Nonvolatile Memory with Ultra Thin Oxide”, Extended Abstracts of the 2001 International Conference on Solid State Devices and Materials, Tokyo, 2001, pp. 532-533.

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