Direct read of DRAM cell using high transfer ratio

Details Direct read of DRAM cell using high transfer ratio Direct read of DRAM cell using high transfer ratio

2002-08-26

2004-05-18

Le, Thong Q. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Precharge

C365S189040

Reexamination Certificate

active

06738300

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to sensing circuits for performing a direct read of a DRAM cell using a high transfer ratio (C
cell
/(C
b1
+C
cell
)), and more particularly pertains to sensing circuits for performing a direct read of a DRAM cell using a high transfer ratio and a single ended read of a single bitline.
2. Discussion of the Prior Art
Conventional DRAMs use sensing schemes that require amplifiers capable of sensing small sense signals. The most effective way to amplify small sense signals has been shown to be a cross-couple sense amplifier, as is well known in the art. These cross-couple sense amplifiers require balanced true and complement bitlines to perform and operate reliably.
Conventional DRAM sensing schemes use destructive read operations, and frequently have a pair of local bitlines BL
0
, BL
1
connected through a gate to a pair of global bitlines GL
0
, GL
1
, which are differentially connected to a secondary sense amplifier. The secondary sense amplifier is differentially connected to the far ends of the global bitlines GL
0
, GL
1
, and is generally a gain device. In contrast thereto, the direct read DRAM circuits of the present invention do not use differentially connected local bitlines BL
0
, BL
1
and global bitlines GL
0
, GL
1
, but instead use a single ended read of a single bitline BL
0
, GL
0
, with four transistor devices.
In conventional DRAMs, the sense signal from a memory cell is generated by charge sharing the charge stored in the memory cell with a precharged bitline, and then comparing the developed sense signal on the precharged bitline to a reference bitline.
To achieve maximum density, a large number of memory cells are typically connected to a single bitline to reduce the area overhead of the amplifier. However, adding cells to a bitline also increases the bitline capacitance, and consequently reduces the transfer ratio (C
cell
/(C
b1
+C
cell
)), which in turn reduces the developed sense signal. Typically the number of bits (memory cells) per bitline is chosen to minimize the number of sense amps (overhead) while maintaining enough sense signal to reliably detect the stored state of a memory cell.
The amplitude of the sense signal &Dgr;Vb
1
from a memory cell is a function of the cell capacitance, the bitline capacitance and the voltage swing to the bitline high precharge, as set forth in the following formulas which includes the transfer ratio.
&Dgr;
Vb
1
=(
V
cell
−V
b1h
)*(
C
cell
/(
C
b1
+C
cell
)), and
where V
cell
=voltage stored in the memory cell
V
b1h
=bitline precharge level voltage (typically 1.2-1.8V)
C
b1
=cell capacitance
C
b1
=bitline capacitance
SUMMARY OF THE INVENTION
Accordingly, it is a primary object of the present invention to provide a direct read of a DRAM cell using a high transfer ratio and a single ended read of a single bitline.
A further object of the subject invention is the provision of direct read DRAM circuits which use a single ended read of a single bitline with four devices (N
2
, N
3
, N
4
, P
0
in FIG.
1
), with three devices preferentially being nFETs.
In accordance with the teachings herein, the transfer ratio of a memory cell (C
cell
/(C
b1
+C
cell
)) is increased from a typical prior art value of 0.2 to be substantially close or equal to 0.5, which equates to roughly 64 bits (memory cells)/bitline, compared to typically 256 bits/bitline for cross-couple sensing as in the prior art. With a transfer ratio of 0.5, a stored high level of 800 mV and a bitline precharge of GND, the voltage level generated on the bitline would be approximately 400 mV, enough to turn on a standard logic NFET device with a threshold voltage of 250 mV which provides sufficient gain to drive a heavy global bitline.
A sensing circuit for performing a direct read of a DRAM memory cell by using a high transfer ratio and a single ended read of a single bitline, wherein a limited number of memory cells are connected to the single bitline to limit the capacitance thereof to provide the high transfer ratio. The direct read circuit includes four transistor devices, with three devices preferentially being nFETs. The direct read circuit provides a self-timed write back of data to a memory cell after the data is destructively read from the memory cell in a read operation, provides significant electrical power savings relative to prior art read circuits, as a read operation of a data
0
does not utilize any significant electrical power, and in a folded bitline architecture provides improved noise immunity as each non-active bitline shields an adjacent active bitline.


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