Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2003-09-10
2004-09-28
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S301000, C438S174000
Reexamination Certificate
active
06797555
ABSTRACT:
TECHNICAL FIELD
The present invention relates to the implantation of fluorine directly into the channel region of a PMOS transistor structure to improve the 1/f noise and V
T
drift margin of the device performance.
BACKGROUND OF THE INVENTION
Mixed signal integrated circuits find the option of dual (or more) gate oxide processes attractive in that multiple voltages can then be used on the same chip. This technique requires that gate oxides be grown twice, to result in different gate oxide thicknesses, and often with different well implantations, so as to provide optimal performance for both the high voltage and the low voltage transistors.
Hook et al., “The Effects of Flourine on Parametrics and Reliability in a 0.18&mgr;m 3.5/6.8 nm Dual Gate Oxide CMOS Technology”, IEEE Transactions on Electron Devices, Vol. 48, No. 7, July 2001, pp. 1346-1353, discuss the benefits of the introduction of fluorine into gate oxide by implantation into the gate polysilicon in PMOS devices.
For reasons of mask count reduction, and thus cost, it is attractive to make use of common source-drain implants, spacer formation and silicidation processing, which are common to both high and low voltage transistors.
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“The Effects of Fluorine on Parametrics and Reliability in a 0.18-&mgr;m 3.5/6.8 nm Dual Gate Oxide CMOS Technolgoy”.
Terence B. Hook et al.; IEEE Transactions on Electron Devices, vol. 48, No. 7, Jul. 2001; pp 1346-1353.
Chaparala Prasad
Hopper Peter J.
Lindorfer Philipp
Vashchenko Vladislav
Lindsay Jr. Walter L.
National Semiconductor Corporation
Niebling John F.
Stallman & Pollock LLP
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