Direct alignment scheme between multiple lithography layers

Details Direct alignment scheme between multiple lithography layers Direct alignment scheme between multiple lithography layers

2006-08-07

2009-06-16

Malsawma, Lex (Department: 2892)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S586000, C438S597000, C257SE21627, C257SE21641, C257SE21658

Reexamination Certificate

active

07547597

ABSTRACT:
A method for directly aligning multiple lithography masking layers. The method may be used to fabricate a flash plus logic structure. The flash plus logic structure may comprise a flash memory cell, a logic cell and a transistor.

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VLSI Technology, edited by S.M. Sze, Copyright 1983—Bell Laboratories, Incorporated, Murray Hill, New Jersey; McGraw-Hill Book Company, ISBN 0-07-062686-3, McGraw-Hill series in electrical engineering, Electronics and electronic circuits; Lithography pp. 273-274.

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