Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-01-16
2004-08-03
Tran, Minhloan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S358000, C257S360000, C257S361000, C257S362000, C257S363000, C257S173000
Reexamination Certificate
active
06770938
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to semiconductor devices and, more particularly, relates to electrostatic protection devices for integrated circuits
BACKGROUND OF THE INVENTION
Electro-static discharge (ESD) or electrical overstress (EOS) is an increasingly significant problem in integrated circuit design as pin counts and faster circuit speeds compound the need for reliable ESD protection. ESD refers to the phenomena whereby a high energy electrical discharge of current is produced at the input and/or output nodes of an integrated circuit as a consequence of static charge build-up on an IC package. The static charge build up can be as a result of a human body handling the IC or due to static charge build up from IC manufacturing handling equipment. Electrostatic discharge has the potential to disable or destroy an entire integrated circuit. Therefore, much effort has been spent in designing adequate ESD protection devices. Ideally, an ESD protection device should be able to discharge an extremely large potential across any two pins of an IC in a nondestructive manner.
Typically, the first circuitry electrically connected to the integrated circuit pads is some type of input/output buffer or level shifter circuit. These devices serve to buffer the logic devices on the integrated circuit and bear the brunt of the ESD problems. In the case of Complimentary Metal Oxide Semiconductor (CMOS) integrated circuit design, the CMOS devices in the integrated circuit will be buffered from the input/output pads by one or more CMOS inverters having wide Field Effect Transistors (FETS) which serve to buffer the internal logic gates from the input/output pad. Therefore, in a typical ESD event, a high voltage applied to an input/output pad would result in a high discharge current to flow through one of the transistors of the CMOS inverter gate to V
DD
or V
SS
, respectively. One type of discharge path may occur from the output pad through a channel FET to V
SS
. Depending upon the polarity of the ESD voltage pulse supplied at the pad, the discharge may either proceed via an avalanche breakdown of the drain/channel junction of the n channel FET or via a forward biasing of the drain/channel diode. The avalanche breakdown type of discharge path is the most destructive since it is most likely to result in irreversible damage to the structure of the n channel FET.
One difficulty in designing ESD protection circuits is the demanding performance requirements that must be met. For example, one of the primary industry standards for measuring robustness is the military standard method MIL-STD-883C method 3015.7 Notice 8 (1989) and its follow on Human Body Model (HBM) standard no. 5.1 (1993) from the EOS/ESD Association. Both of these standards require ESD zapping for what can be a large number of pin and power supply combinations. ICs have come under pressure in HBM tests because of repeated stressing of the power supply rails leading to wear out of various breakdown points, such as the V
CC
lines. A reliable powers supply clamp is needed to reduce the susceptibility of the V
CC
power bus failure mechanism. One conventional methodology relied on in designing protection circuits is known as the snap-back phenomena. The snap-back phenomena refers to the use of a junction breakdown to control current and voltage behavior in the manner of a voltage clamp. A snap-back device is designed to keep the voltage low enough to protect sensitive gate dielectrics.
FIG. 1
illustrates one conventional system
10
of peripheral circuitry employing ESD devices utilizing the snap-back phenomena. A pad
34
is coupled to a buffer or level shifting circuit
15
comprised of a PMOS transistor
16
and an NMOS transistor
18
configured as a complimentary CMOS inverter. The PMOS transistor
16
includes a gate oxide layer
17
and the NMOS transistor
18
includes a gate oxide layer
19
. The output of the CMOS inverter
15
is coupled to circuitry (not shown) in the die core. A power supply clamp device
20
is coupled between V
CC
and V
SS
for protecting the power supplies from an ESD event. The power supply clamp device
20
is comprised of a bipolar junction transistor (BJT)
24
with a diode
26
connected in parallel across the collector of the BJT
24
. A capacitor
30
is coupled to the base of the BJT
24
and the supply V
CC
and a resistor
28
is coupled to the base of the BJT
24
and the supply V
SS
. A capacitor
22
is coupled to the supply V
CC
and the supply V
SS
. An input protection circuit
11
comprises a first diode
12
with its cathode coupled to the supply V
CC
and its anode coupled to the pad
34
and a second diode
14
with its anode connected between the supply V
SS
and its cathode connected to the pad
34
. During a negative polarity ESD stress applied between the pad
34
and the V
CC
supply
32
, some of the current follows the path
35
along the arrows through the NMOS transistor
18
and the diode
26
back to the supply V
CC
. Since the diode
14
has a reverse break down voltage of about 12-13 volts and the break down voltage of the gate oxide layers
17
and
19
are about 9-10 volts, there is potential for damage to the gate oxide layer
19
along the current path
35
, until the ESD voltage reaches 12-13 volts and the diode
14
begins to conduct in the reverse breakdown region. The ESD circuit of the system
10
also requires the diode
26
, so that the current path
35
can flow to the supply V
CC
. Therefore, the diode
26
is necessary and takes up additional space on the IC die. If a positive stress is applied to V
CC
the current will discharge through the BJT
24
along the path
37
. However, the BJT
24
switches slowly and sometimes still results in damage to the integrated circuit. Other problems with the use of a BJT is that the device takes up a great deal of space on the integrated circuit die and is not conducive to scalability as other devices shrink in size.
SUMMARY
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended to neither identify key or critical elements of the invention nor delineate the scope of the invention. Its sole purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The present invention relates to an ESD protection device for an integrated circuit. The ESD protection device includes a power supply clamp device formed from a diode and coupled between a first power supply V
CC
and a second power supply V
SS
. An input protection device is also provided which is formed from a diode coupled between an input pad and the first power supply and a second diode coupled between the input pad and a second power supply. The diodes have an adjusted reverse breakdown voltage that is higher than the voltage supply V
CC
used to power the peripheral circuitry that drives circuitry within a core of the integrated circuit. The adjusted reverse breakdown voltage is also lower than the breakdown voltage of gate oxide layers used within the peripheral circuitry.
In one aspect of the invention, the diodes are formed by providing heavily doped N
++
and P
++
regions in a p-substrate to adjust the reverse breakdown voltages of the diodes. The diode can be formed in a guard ring of the integrated circuit device without requiring additional real estate on the integrated circuit device. The heavily doped regions are provided by first providing a P
+
implant into an active region of a peripheral region of an integrated circuit device to form a P
++
region in the p-substrate. A first N
+
implant is then performed into a portion of the P
++
region to form a N
+
region. A second implant is then performed into the N
+
region to form the heavily doped N
++
region. Various connections may be provided to the N
++
Fliesler Michael
Kuo Paohua
Morgan Ian
Ramsbey Mark
Randolph Mark
Advanced Micro Devices , Inc.
Amin & Turocy LLP
Dickey Thomas L
Tran Minhloan
LandOfFree
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