Digital timing recovery using baud rate sampling

Details Digital timing recovery using baud rate sampling Digital timing recovery using baud rate sampling

1999-08-31

2002-11-26

Butler, Dennis M. (Department: 2185)

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

C713S600000, C360S051000

Reexamination Certificate

active

06487672

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to reading of information from a storage medium and more particularly to a storage medium read channel employing interpolated timing recovery.
BACKGROUND OF THE INVENTION
The need to increase the storage density of information storage media, such as magnetic and optical storage media, is a well-known goal in the art. In a typical magnetic storage media device, information is written onto the medium as a series of pulses, which pulses are recorded as magnetic bit cells of either a positive or negative polarity. The pulses are then read using a coil, such as a read/write head, whereby the transitions in the polarity between adjacent bit cells cause an analog signal in the coil as the read/write head passes over the magnetic medium. The analog signal can then be coded into a digital signal using well-known digital sampling techniques.
As the analog signal is converted to a digital signal, it is important to properly align the sampling rate and phase to the rate and phase at which the information was originally written. This is important so as to ensure accurate detection of the pulses that were written to the medium. The rate at which the signal was written to the storage medium is typically referred to as the baud rate.
Accurate sampling at the baud rate and with minimal phase shift is necessary in order to minimize inter-symbol interference, as well. As storage density has increased, with the bit cells being placed closer together, the need to accommodate inter-symbol interference has become increasingly important.
Sample rate and phase variations can be compensated for in two general ways. In the first method, the phase difference between the sampled values and expected values is detected, and the sampling clock, typically a variable frequency oscillator (VFO) is adjusted in order to minimize or eliminate the phase difference, using a frequency feedback loop. Several VFOs may be required, however, one for the write channel, and one or more may be required for the read channel if information is written to the storage medium at different nominal baud rates, which is often the case. These multiple VFOs may give rise to cross-talk interference. More importantly, the VFO requires analog circuitry for its implementation. Analog circuitry is much more susceptible to process variations affecting circuit performance. Likewise, analog circuitry is not as easily migrated to new semiconductor processes which is an additional disadvantage. Circuit test is also more difficult with analog circuits than with comparable digital circuits.
A digital circuit based method of compensating for frequency and phase errors employs digital interpolation to minimize phase errors. In the digital interpolation method, the analog signal is sample asynchronously to the baud rate. The phase difference between the sampled values and expected values is again detected, but this phase error signal is used to adjust the interpolation interval of an interpolating timing recovery circuit. The interpolating timing recovery circuit generates interpolated sample values that are substantially synchronous to the baud rate. Because the interpolating timing recovery circuit does not require adjusting the sampling rate, the need for multiple VFOs is eliminated.
Because the interpolating timing recovery circuit samples asynchronously, however, an oversampling condition or undersampling condition is likely to result. In an oversampling condition, the sampling frequency exceeds the baud rate. As a result, the period between successive sample points must be extended in order to synchronize to the baud rate. In the undersampling condition, the sampling frequency is less than the baud rate, and the interpolator circuitry must decrease the period between successive sample points. Because the sampling is done asynchronously, the circuitry has no way of knowing whether it is in an oversampled or undersampled condition, however.
In order to address this issue, prior art methods have been employed in which the sampling rate is selected at a frequency that is known to be higher than the baud rate. For instance, Spurbeck et al., in U.S. Pat. No. 5,696,639, disclose an interpolating timing recovery circuit in which the sampling rate is selected to always be 1% to 2% higher than the write clock or baud rate. In that way, the read channel is known to always be operating in an oversampling condition. Once this is known, techniques can be employed to compensate for the oversampling condition, as is disclosed in the referenced patent.
The drawback in forcing an oversampling condition at all times is that this requires two separate synthesizers, one for the baud rate clock and one for the read channel clock. These two clocks must be close in frequency, say within 2%, at each of the frequencies at which data may be written to the storage medium (e.g. different baud rates may be employed at different locations on the storage medium). Because the synthesizers are analog circuits, the circuits are sensitive to process and other variations that might skew the frequencies of the clocks relative each other.
Therefore a need exists in the art for an efficient interpolating timing recovery circuit that can accommodate an asynchronous sampling clock that is nominally at the baud rate and that can compensate for both oversampling and undersampling conditions that may arise from differences in the baud rate and the sampling rate.
SUMMARY OF THE INVENTION
The present invention provides a device for reading information stored on a medium by detecting data from a sequence of discrete time interpolated sample values. The interpolated sample values are generated by interpolating a sequence of discrete time channel sample values generated by sampling pulses in a read signal from the medium. The device includes a sampling clock outputting a clock signal with a period of T and a sampling device, responsive to the sampling clock, receiving as input the read signal and outputting the channel sample values. An interpolated timing recovery circuit receives as input the channel sample values and outputs the interpolated sample values. The interpolated timing recovery circuit includes an accumulator for generating, modulo-T, a fractional delay value. An elastic buffer receives as input and stores the interpolated sample values from the interpolated timing recovery circuit. The interpolated sample values are subsequently read out to a data detector. In response to detection that the fractional delay value has wrapped past its maximum value through its minimum value, the elastic buffer prevents one interpolated sample value from being read out to the data detector; and in response to detection that the fractional delay value has wrapped past its minimum value through its maximum value, the elastic buffer stores one interpolated sample value and one associated channel sample value.


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Floyd M. Gardner, Interpolation in Digital Modems—Part I: Fundamentals,IEEE Transactions on Communications, 41(3), Mar. 1993.
Floyd M. Gardner, Interpolation in Digital Modens—Part II: Implementation and Performance,IEEE Transactions on Communications, 41(6), Jun. 1993.

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