Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-02-06
2007-02-06
Chung, Phung My (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S741000, C714S047300
Reexamination Certificate
active
10518743
ABSTRACT:
A method of optimising a digital test signal for testing an analogue or mixed-signal circuit comprising determining a measure, for example a figure of merit, that is indicative of differences between the output of a fault free and the output of a known faulty circuit in response to an applied digital input signal. The digital input signal is then varied and another figure of merit is calculated for the fault free and the known faulty circuit for the new input signal. This is repeated a number of times, the digital input signal being varied each time. An optimum test signal is selected based on the determined figures of merit.
REFERENCES:
patent: 5694356 (1997-12-01), Wong et al.
patent: 5745409 (1998-04-01), Wong et al.
patent: 5748124 (1998-05-01), Rosenthal et al.
patent: 5793778 (1998-08-01), Qureshi
patent: 6467058 (2002-10-01), Chakradhar et al.
patent: 6898746 (2005-05-01), Jain et al.
patent: 2002/0188904 (2002-12-01), Chen et al.
patent: WO 98/55880 (1998-12-01), None
Zheng et al.;A Novel Test Generation Approach for Parametric Faults in Linear Analog Circuits; 14th IEEE VLSI Test Symposium; 1996; pp. 470-475 (XP-002265465).
Saab et al.;CRIS: A Test Cultivation Program for Sequential VLSI Circuits; IEEE; 1992; pp. 216-219.
Van Spaandonk et al.;Selecting Measurements to Test the Functional Behavior of Analog Circuits; Journal of Electronic Testing: Theory and Applications; 1996; pp. 9-18; vol. 9; Kluwer Academic Publishers, The Netherlands (XP-000636621).
Balivada et al.;A Unified Approach for Fault Simulation of Linear Mixed-Signal Circuits; Journal of Electronic Testing: Theory and Applications; 1996; pp. 29-41; vol. 9; Kluwer Academic Publishers, The Netherlands (XP-000636623).
Souders, et al.,Accurate Frequency Response Determinations from Discrete Step Response Data; IEEE Transactions on Instrumentation and Measurement; Jun. 1987; pp. 433-439; vol. IM-36, No. 2.
Eckersall, et al.,Testing an Analogue Circuit Using a Complementary Signal Set; IEE Colloquium on Testing Mixed Signal Circuits, 1992; pp. 5/1-5/6; Digest No. 1992/118.
Al-Qutayri, et al.,Go
o-go Testing of Analogue Macros; IEE Proceedings; Aug. 1992, pp. 534-540; vol. 139, No. 4.
Pan, et al.;Pseudorandom Testing for Mixed-Signal Circuits; IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems; Oct. 1997; pp. 1173-1185; vol. 16, No. 10.
Variyam, et al.;Digital-Compatible BIST for Analog Circuits Using Transient Response Sampling; IEEE Design & Best of Computers; Jul.-Sep. 2000; pp. 106-115.
Hooke, et al.;“Direct Search” Solution of Numerical and Statistical Problems; May 1960, revised Oct. 1960; pp. 212-229; Westinghouse Research Laboratories; Pittsburgh, Pennsylvania.
Search Report for International Application No. PCT/GB03/02599 completed Apr. 20, 2004.
International Preliminary Examination Report for International Application No. PCT/GB03/02599 completed Nov. 2, 2004.
Bekheit Mahmoud Ali Mousa
Hamilton David James
Stimpson Brian Philip
LandOfFree
Digital system and method for testing analogue and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Digital system and method for testing analogue and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Digital system and method for testing analogue and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3857288