Digital signature generation for hardware functional test

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C714S045000, C714S716000, C714S733000, C714S724000, C714S734000, C714S750000, C714S718000

Reexamination Certificate

active

07461312

ABSTRACT:
A Multiple Input Shift Register (MISR) is used to generate signatures, based on data from a device under test, in order to validate the proper sequence and content of the data over a defined period of time. The MISR described herein includes the ability to “tag” the signatures for each time period using an incrementing value, and make that tag and the signature readable by a test controller. The MISR has the flexibility to be reset to a known initial state (or otherwise load a seed value) at the beginning of each time period or to continue accumulating signatures without being reset (or using the seed value). Accumulation of signatures over an extended period of time allows a test controller to validate that no errors occurred during a long term test without having to closely monitor the intermediate results.

REFERENCES:
patent: 4601033 (1986-07-01), Whelan
patent: 4801870 (1989-01-01), Eichelberger et al.
patent: 5383143 (1995-01-01), Crouch et al.
patent: 5412665 (1995-05-01), Gruodis et al.
patent: 5416783 (1995-05-01), Broseghini et al.
patent: 5488615 (1996-01-01), Kunoff et al.
patent: 5784383 (1998-07-01), Meaney
patent: 6249893 (2001-06-01), Rajsuman et al.
patent: 6311311 (2001-10-01), Swaney et al.
patent: 6490702 (2002-12-01), Song et al.
patent: 6587963 (2003-07-01), Floyd et al.
patent: 6671839 (2003-12-01), Cote et al.
patent: 6684357 (2004-01-01), Im
patent: 6782501 (2004-08-01), Distler et al.
patent: 6807646 (2004-10-01), Williams et al.
patent: 6829740 (2004-12-01), Rajski et al.
patent: 2003/0115525 (2003-06-01), Hill et al.
patent: 2003/0223397 (2003-12-01), Iacono et al.
patent: 2004/0107395 (2004-06-01), Volkerink et al.
patent: 2004/0133832 (2004-07-01), Williams et al.
patent: 2004/0216061 (2004-10-01), Floyd et al.
Gosh, et al., “A BIST Scheme for RTL Controller-Data Paths Based on Symbolic Testability Analysis,” pp. 554-559, Jun. 15-19, 1998, ISBN, San Francisco, CA, USA.
Hosokawa, et al., “Design for Testability Strategies Using Full/Partial Scan Designs and Test Point Insertions to Reduce Test Application Times,” pp. 485-491, 2001 IEEE.
Kishinevsky, et al., “Partial Scan Delay Fault Testing of Asynchronous Circuits,” pp. 728-735, 1997 IEEE.
Mukherjee, “Design for Testability to Achieve High Test Coverage,” IEEE Symposium on Defect and Fault Tolerance, pp. 1-9, Wipro Technologies, 2000 IEEE, Japan.
Nourani, et al., “Integrated Test of Interacting Controllers and Datapaths,” ACM Transactions on Design Automation of Electronic Systems, Jul. 2001, vol. 6, No. 3, pp. 401-422.
Tsai, et al., “Improving the Test Quality for Scan-based BIST Using a General Test Application Scheme,” 6 pgs., 1999 ACM, New Orleans, LA, USA.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Digital signature generation for hardware functional test does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Digital signature generation for hardware functional test, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Digital signature generation for hardware functional test will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4042454

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.