Electronic digital logic circuitry – With test facilitating feature
Reexamination Certificate
2001-04-10
2002-12-03
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
With test facilitating feature
C326S093000, C326S099000
Reexamination Certificate
active
06489802
ABSTRACT:
TECHNICAL FIELD
The invention relates to signal processing and device testing involving high-speed digital signals. In particular, the invention relates to reducing input transition rates when performing signal processing with digital devices and during testing of high-speed digital devices.
BACKGROUND ART
Clock rates in digital systems and the semiconductor devices or integrated circuits (ICs) that invariably make up the systems continue to increase. Associated with the increases in clock rates is an increase in data rates of signals generated by the digital systems. The data rate of a digital signal is proportional to the rate of logic transitions found in the signal and is sometimes referred to as the transition rate. Increases in transition rates of signals produced by modem digital systems are expected to continue for the foreseeable future.
Rapid or high transition rates typical of the signals generated by modem digital systems pose a problem for components and systems that must receive and process these signals. As transition rates increase, the cost and complexity of these so-called ‘downstream’ components and systems tend to increase dramatically. In an analogous manner, fast transition rates of the signals generated by modem digital systems also significantly increase the difficulty of adequately and accurately testing these systems. At the very least, the fast transition rate of the high speed signals tend to significantly increase the cost of the test equipment required for adequate testing. In addition, relatively expensive test equipment is often rendered obsolete by increases in transition rates over time. Obsolescence of modem test equipment associated with transition rate increases can occur in a very short time given the current frenetic pace of clock and transition rate increases.
To avoid the use of high speed, expensive downstream components and to avoid the need for upgrading or replacing test equipment to accommodate increases in transition rates, it is sometimes attractive to employ approaches to signal processing and/or testing that attempt to reduce the maximum transition rates of the signals of interest. In essence, the maximum transition rate experienced by downstream components and/or test equipment can be reduced in some cases by inserting a transition rate-reducing device between the component or piece of test equipment and the digital system generating the signal. If the transition rate can be reduced while simultaneously maintaining the integrity of the data contained in the signal, lower cost components can be used to process the signal and/or test the device that generated the signal. The discussion that follows, while focusing on test equipment for simplicity, applies equally well to any downstream component that must receive and process high-speed signals.
One approach to reducing transition rates is known as frequency division. This approach is most effective for signals, such as clock signals that are relatively narrowband. A device known as a frequency divider reduces the frequency or transition rate of a signal. Typically, frequency dividers for digital signals are implemented using one or more flip-flops and provide integer division of the input frequency. However, this approach is not particularly useful for signals that contain data since these signals are typically not narrowband. Moreover, frequency division of signals that contain data typically results in the loss of some of the data of the signal. Loss of data is normally unacceptable. Thus, this technique is most often used for reducing the transition rate of signals, such as clock signals, that contain little or no data. The concept of frequency division of a clock signal is illustrated in FIG.
1
A. In
FIG. 1A
, a frequency divider
10
with a division factor of two is illustrated operating on a clock signal.
Another approach to transition rate reduction, sometimes referred to as ‘sampling’, employs a waveform sampler between the device under test (DUT) and the test equipment. The signal is sampled by the waveform sampler to produce two or more sub-signals, each containing a portion of the data contained in the original, higher speed signal. The two or more sub-signals each have a lower transition rate than the original signal. Several parallel channels within the test equipment then process the sub-signals. For example, in one implementation, odd numbered samples of the waveform are contained in a first sub-signal and are processed by a first channel, while even numbered samples are contained in a second sub-signal and are processed by a second channel. Typically the channels of the test equipment operate in parallel to simultaneously process the sub-signals.
The sampling concept is illustrated in FIG.
1
B and FIG.
1
C. As illustrated in
FIG. 1B
, a signal under test S
in
is sampled by a sampler. The sampler is clocked by a clock signal CLK and samples are taken at both the rising and falling edges of the clock signal. The sampler produces two sub-signals A and B as illustrated in FIG.
1
B. Sub-signal A represents the amplitudes of samples of the signal under test S
in
at odd numbered sample intervals corresponding in this case to rising edges of the sampling clock signal CLK. Sub-signal B represents samples at even numbered sample intervals taken at falling edges of the clock signal CLK. Two parallel channels are used in the test equipment (not illustrated) to simultaneously process the sub-signals A and B. Once processed, bit level information of the original signal under test can be extracted. The effective transition rate reduction for the example illustrated is a factor of two. Further reductions in the maximum transition rate can be ,realized with the addition of more parallel channels, more delayed versions of the clock signal CLK, and more sub-signals.
FIG. 1C
illustrates one implementation of a sampler
20
. As illustrated, the sampler comprises a first D flip-flop
22
and a second D flip-flop
24
. The signal under test S
in
is applied to data inputs of the first and second D flip-flops
22
,
24
. The sampling clock signal CLK is applied to a clock input of the first D flip-flop. An inverse of the clock signal CLK is applied to a clock input of the second D flip-flop
24
. Each rising edge of the clock signal CLK causes the first D flip-flop
22
to sample the signal S
in
while each falling edge of the clock signal causes the second D flip-flop
24
to sample the signal S
in
. The sub-signals A and B are output at outputs Q of the first and second D flip-flops
22
,
24
respectively.
The samples in the sampling approach described hereinabove are generally treated and can be viewed as two or more interleaved signals from a processing standpoint. Typically in this approach, the sampler measures signal amplitude at each sample point. Therefore, information regarding digital signal transition timing is generally unavailable except at a coarse level. In addition, careful synchronization of the sampler and the signal under test is often required to insure the validity and usefulness of the samples in the sub-signals.
Accordingly, it would be advantageous to have an apparatus and method for use in testing and/or processing of digital signals that significantly improved the frequency scalability of test equipment or downstream communications signal processing components, for example, by reducing the maximum transition rate of the signals. In addition, it would be desirable that such an apparatus and method, while reducing the maximum transition rate of the signal, preserved transition timing information of the signal, thereby enabling precision timing tests to be performed on the DUT or enabling downstream precision signal processing. Moreover, it would be desirable that such an apparatus and method could be realized without requiring tight synchronization to the signal under test or the use of a synchronized clock signal and that such an apparatus and method could be implemented using standard, readily available components. Such an apparatus and method would
Khoche Ajay
Rivoir Jochen
Agilent Technologie,s Inc.
Tokar Michael
Tran Anh Q.
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