Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-06-21
2002-07-23
Beausoleil, Robert (Department: 2184)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S030000, C714S034000
Reexamination Certificate
active
06425102
ABSTRACT:
FIELD OF THE INVENTION
The present invention pertains to a digital signal processor (hereafter called DSP) that is a processor specifically developed for high-speed digital signal processing of grouped digital signals, and in particular, it pertains to an improvement in DSP operation testing.
BACKGROUND OF THE INVENTION
Conventional DSPs are explained below. In
FIG. 3
, symbol
101
is a conventional DSP. This DSP
101
has external input terminals
111
-
113
, DSP circuit
102
, interface circuit
103
, and external output terminals
131
-
133
. This DSP
101
is constituted so that when external input terminals
111
-
113
are connected to the output terminal of an external device, such as a digital modem, and external output terminals
131
-
133
are connected to the input terminal of an external device, signals output by an external device are input into interface circuit
103
and signals that are output from interface circuit
103
can be input into an external device via external output terminals
131
-
133
. Note that in
FIG. 3
only external input terminals
111
-
113
and external output terminals
131
-
133
are shown, but more external input terminals and external output terminals can be provided.
Interface circuit
103
is a circuit that converts input signals into a form that can be processed by DSP circuit
102
. In normal operation, signals are input into DSP circuit
102
after conversion, and after arithmetic processing is performed by the DSP core
104
in DSP circuit
102
, they are output to interface circuit
103
.
Then interface circuit
103
converts the arithmetically processed results input from DSP circuit
102
and outputs them to an external device via external output terminals
131
-
133
, and therefore the entire DSP
101
is able to control the external device.
As an example of a case where operation testing is performed before a DSP
101
such as this is installed, instead of an external device, a tester, which is not shown, is connected to external input terminals
111
-
113
and to external output terminals
131
-
133
, specific signals are input from this ester to external input terminals
111
-
113
, and signals output from external output terminals
131
-
133
are read by the tester. By determining if the output signals agree with predetermined specifications, it can be determined whether DSP
101
is operating correctly.
However, there are problems with the aforementioned operation testing of DSP
101
. Specifically, signals are transmitted via interface circuit
103
, so even if it is determined that the operation of DSP
101
is abnormal, it is impossible to determine whether this is due to a faulty DSP circuit
102
or due to a faulty interface circuit
103
, and since DSP circuit
102
cannot be coupled directly to the tester, the operation of DSP circuit
102
alone cannot be tested.
So, self-testing, in which the DSP circuit
102
tests its own operation by producing test data inside the DSP circuit
102
, bypassing interface circuit
103
, has been proposed.
In order to execute this self-testing, data transfer circuit
105
, memory
106
, data hold circuit
107
, and multiplexer
120
are provided for DSP circuit
102
.
With self-testing, during test setup, test programs, and setting information required for test data production are written to memory
106
from DSP core
104
. After this, when test execution has started, test programs, setting information, etc. are supplied to DSP core
104
from memory
106
.
Next, test data and control instructions with the same specifications as data input to DSP core
104
during normal operation are produced by DSP core
104
based on the test programs and output to data transfer circuit
105
. Test data and control instructions are output to multiplexer
120
from each data line L
111
and L
112
in data line group
140
from data transfer circuit
105
.
Multiplexer
120
, during actual operation, connects output signal line group
150
of interface circuit
103
to DSP core
104
, but during test operations it connects data line group
140
to DSP core
104
based on control instructions output from DSP core
104
. Consequently, the test data generated by data transfer circuit
105
are input to input terminals IN
1
and IN
2
of the DSP core.
Input test data are arithmetically processed by DSP core
104
and the results of the arithmetic processing are output to data line group
160
from output terminals T
1
and T
2
. The arithmetic processing results output to data line group
160
are held by data hold circuit
107
and output in a specific order to input terminal TDI on DSP core
104
. Finally the output is re-input to DSP core
104
.
The arithmetic processing results input to input terminal TDI are compared with the correct arithmetic processing results already held in DSP core
104
and it is determined whether the arithmetic processing that was performed was correct or not. After this, new test data are produced by DSP core
104
, and the sequence of arithmetic processing and evaluation processing discussed above is repeated the exact number of predetermined times. When all the executed arithmetic processing results equal the correct arithmetic processing results, the DSP circuit
102
is judged to be good by the DSP core
104
itself. Then, by outputting the results of this evaluation from data line L
r
. to an external circuit, which is not shown, self-testing is completed.
In this way, self-testing has the advantage that the DSP circuit
102
can be tested while bypassing interface circuit
103
, so it is possible to test only the DSP circuit
102
, which would have been impossible with operation testing using a tester.
Also, there is a halt terminal HALT, which is an operation halt/continue control terminal for DSP core
104
, in DSP core
104
, and there is a test that determines whether the operation of DSP
101
can be halted normally by means of halt terminal HALT (hereafter called hold testing).
When hold testing is performed by self-testing, halt terminal HALT and data transfer circuit
105
are connected via multiplexer
120
, DSP core
104
outputs a halt signal via data transfer circuit
105
, and the halt signal is input to halt terminal HALT. When a stop signal is input to halt terminal HALT, the operation of DSP core
104
itself is halted. The result is that not only is it impossible for the DSP core
104
itself to determine whether the halt state is good, but processing cannot be restarted.
The present invention was created to solve problems such as these in the prior art. Its objective is to provide a digital signal processor DSP, which allows core self-testing, and after the core itself has been halted, it can be determined whether the core's halt state is good by restarting the core.
SUMMARY OF THE INVENTION
In order to solve the aforementioned problems, the digital signal processor described therefor herein is constituted by having a processor for processing digital signals, a memory that holds data for self-testing of the aforementioned processor, a data transfer circuit into which are input self-test control data, which are output by the aforementioned processor for the processor and that supplies the relevant self-test control data to the aforementioned processor, an operation controller into which control signals are input from the aforementioned processor and that supplies operation control signals to the aforementioned processor after a specified time has elapsed, a first switching circuit that is installed between an external input terminal, the aforementioned data transfer circuit and a data input terminal of the aforementioned processor and that selects data supplied from either the aforementioned external input terminal or the aforementioned data transfer circuit and outputs the data to the aforementioned data input terminal, and a second switching circuit that is installed between the aforementioned input terminal, a halt terminal of the aforementioned processor, aforementioned data transfer circuit, and the aforementioned operation control
Beausoleil Robert
Brady III W. James
Chu Gabriel
Laws Gerald E.
Telecky , Jr. Frederick J.
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