Electrical computers and digital processing systems: processing – Instruction alignment
Reexamination Certificate
1998-11-06
2001-12-18
Coleman, Eric (Department: 2183)
Electrical computers and digital processing systems: processing
Instruction alignment
C712S035000
Reexamination Certificate
active
06332188
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to digital signal processors, and more particularly to a digital signal processor with a novel computation block that includes a bit FIFO.
BACKGROUND
A digital signal processor is a special purpose processor optimized for digital signal processing applications such as speech analysis and synthesis to produce computerized speech, image processing, or digital filtering. The digital signal processing applications tend to be intensive in memory access operations and tend to require the input and output of large quantities of data. Real-time digital signal processing requires fast hardware to perform a large number of calculations. In many algorithms, the calculations involve repetitions of a very large number of multiplication and accumulation functions. The number of these calculations, performed in real-time by the processor between individual data samples, may limit the signal processing because it limits the sampling rate. Thus, the processor is designed for high throughput numerical processing and high interrupt rates.
In general, a digital signal processor includes a core processor, at least one memory for storing instructions and operands used in operations, link port buffers for communicating with communication ports and an external port for controlling communications via an external data bus and an external address bus. The core processor includes a control block, an instruction alignment buffer connected to a primary instruction decoder, and at least one computation block for performing the digital signal processing operations. The computation unit includes a register file, a multiplier/accumulator, an arithmetic logic unit (ALU), and a shifter. The core processor may use several different computational schemes and data storage and transfer schemes for optimizing speed, accuracy, size and performance.
Usually, the shifter operates on data organized as n-bit words. The shifter receives instructions from the sequencer, receives operands from the register file, and stores operands in the register file, all operations occurring on n-bit boundaries. For example, the shifter performs a left shift in which the i-th bit is replaced by the (i+1)st bit, and performs a right shift in which the i-th bit is replaced by the (i−1)st bit. In logical shifts, the bit shifted out is lost and the bit shifted in is zero. In circular shifts, the bit shifted out of one end is shifted into the other end, thereby losing no information. In arithmetic shifts, by shifting a bit string left, the shifter multiplies by two the binary number represented by the bit string, and by shifting the bit string right, the shifter divides the binary number by two.
The register file includes a multiplicity of registers having a selected bit size for temporary storage of instructions, operands and results. The register file receives the operands from the memory and provides the operands to the multiplier, the ALU, and the shifter via several operand busses. After computation, the register file receives the results from the multiplier, the ALU, and from the shifter via several result busses. Usually, the multiplier, the ALU and the shifter operate on data that has a fixed word size. However, the fixed word size is not necessarily optimal for all digital signal processing applications.
For example, certain communication applications may use Huffman coding, which uses a variable length character encoding scheme (as opposed to character encoding schemes that use a fixed number of bits per character). The Huffman coding minimizes the total number of bits for characters appearing with the highest frequency. This coding selects the number of bits based on known probabilities so that a data string is decoded as the bits arrive in the data stream. This coding achieves a tighter packing of data since the most commonly occurring characters are short and the infrequently occurring characters are long, wherein the shortest character with the highest probability of occurrence is only one bit long. Most digital signal processors are designed to manipulate data having a fixed word size (e.g., 16-bit or 32-bit words). Such design is not optimal for implementing the Huffman coding.
SUMMARY
The present invention is a digital signal processor with a novel computation block and a method for transferring in a single cycle a bit field of an arbitrary bit length (or words of a variable bit length), wherein the transferred bit field is used for further operations.
A digital signal processor includes a computation block with an arithmetic logic unit, a multiplier, a shifter and a register file. The computation block also includes a plurality of registers for storing instructions and operands in a bit format as a continuous bit stream, and uses a bit transfer mechanism constructed and arranged to transfer in a single cycle a bit field of an arbitrary bit length between the plurality of registers and the shifter.
In one embodiment, the plurality of registers are general purpose registers located in the register file. The register file may further include at least one control information register arranged to store control information used by the bit transfer mechanism.
Preferably, the bit transfer mechanism is further arranged to extract a bit field of a length, specified according to the control information, from a continuous bit stream held in the plurality of registers and store the extracted bit field in the shifter.
Preferably, the register file further includes a pointer register arranged to store a bit pointer, and a length register arranged to store a bit length. The bit transfer mechanism may be further arranged to extract the bit field, having the bit length specified in the length register and being at a location specified by the bit pointer, from the plurality of registers and store the extracted bit field in the shifter. The bit pointer may be arranged to keep track of a current bit position in the continuous bit stream stored in the plurality of registers. The arithmetic logic unit may be arranged to update the bit pointer by the specified length.
Preferably, the arithmetic logic unit updates the bit pointer by the specified length by adding to the bit pointer the specified length and returning to the pointer register modulo of a number that is equal to one half of a capacity of the plurality of registers. The digital signal processor may include a memory and the bit transfer mechanism may be further arranged to conditionally load data from the memory to the plurality of registers. The bit transfer mechanism may be arranged to make the conditional loading permanent when the updated pointer is incremented past a selected bit capacity of the registers. The selected bit capacity may be 64 bits
In another embodiment, the register file includes a pointer register arranged to store a bit pointer, and a length register arranged to store a bit length. The bit transfer mechanism may be further arranged to deposit from the shifter to the plurality of registers a bit field having a bit length specified in the length register and being stored at a location specified by the bit pointer. The bit pointer may be arranged to keep track of a current bit position in the continuous bit stream stored in the general purpose registers. The arithmetic logic unit may be arranged to update the pointer register by the length. The arithmetic logic unit may update the pointer register by the specified length by adding to the bit pointer the specified length and returning to the pointer register modulo
64
of the addition. Alternatively, the arithmetic logic unit may return to the pointer register a number equal to modulo
32
of the addition when the bit capacity of the registers is 32 bits.
Preferably, the bit transfer mechanism may be arranged to conditionally load data from the plurality of registers to a memory of the digital signal processor. The bit transfer mechanism can make the conditional loading permanent when the updated pointer points at a bit number smaller than a bit number of the poi
Fridman Jose
Garde Douglas
Greenfield Zvi
Levine David R.
Lezerovitz Aryeh
Analog Devices Inc.
Coleman Eric
Wolf Greenfield & Sacks P.C.
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