Digital signal processor using a reconfigurable array of macroce

Details Digital signal processor using a reconfigurable array of macroce Digital signal processor using a reconfigurable array of macroce

1998-02-05

2000-07-25

Palys, Joseph E.

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

712221, 712242, 714731, G06F 112

Patent

active

060947268

ABSTRACT:
A real time digital systolic processor with a core of reconfigurable interconnected macrocells which can be programmed according to function for processing high bandwidth digital data. Each macrocell contains arithmetic logic units for performing predetermined functions based on format of the input data stream from an outside source or from other macrocells. The interconnects between each macrocell are arranged so that the function of the device is predetermined according to user specific applications.

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