Electrical computers and digital processing systems: memory – Storage accessing and control
Reexamination Certificate
1998-06-24
2001-06-12
Maung, Zarni (Department: 2154)
Electrical computers and digital processing systems: memory
Storage accessing and control
C711S005000
Reexamination Certificate
active
06247095
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to digital audio processors and, more specifically, to a PCI bus based digital audio processor containing a reverberation system which does not require auxiliary memory and requires low bus overhead.
2. Description of the Prior Art
Digital reverberation processors are known in the art. An audio signal is created which simulates a signal subject to an acoustic reflection in a natural environment by taking a source signal, delaying it by some time corresponding to the apparent distance the sound travels to the reflecting point and adding a portion of that signal to the original source. This can be performed by writing a digital representation of an audio signal into digital memory on a continuous basis utilizing a circular buffer. The signal data is written sequentially into memory until the end of the buffer is reached. The data is then read at a tap location which is a memory location displaced by some relative offset which corresponds to the reverberation time delay. True natural reflections do not consist of a single reflection, but multiple reflections. In order to simulate this, multiple taps are used where the signal has been delayed by differing times. Portions of the signals at each of these time-delay taps are added to the source signal to achieve a resultant signal which corresponds to the desired source in a reverberative environment. In a digital reverberation processing system, the tapped signals are produced by accessing a memory stored image of the source signal at various points in that image corresponding to different instants in time.
In a typical reverberation system within a sound controller for a personal computer, the memory to represent the stored signal to produce these delayed signal taps, known as tank memory, is an external memory device attached to extra pins on the sound controller. The present invention makes it possible to move the tank memory of the reverberator to the main personal computer memory while creating a minimal system performance penalty and without requiring extra pins to interface that memory. This reduces both size and cost of the circuitry required to make a reverberator circuit for a personal computer.
Reverberator systems are needed to produce realistic sound for games and other audio simulations in a personal computer where the ability to reverberate sound can give the game designer the ability to simulate motion of the sound source or the listener. The present invention allows for this function to be easily added within the system components of a personal computer without the added cost of a tank memory separate from the main memory of the personal computer.
The present invention also makes it possible for the tank memory to not be contiguous, but consist instead of a set of pages which are discrete blocks of memory starting at arbitrary locations within the physical memory space of the main personal computer memory. This is an advantage in that large contiguous buffers may not be available in a personal computer systems. Modern operating systems allocate physical memory in blocks and are mapped as virtual addresses. This creates a situation where available memory may have gaps that are allocated to other processes in the computer and a large contiguous buffer may not be available when the reverberation processor is needed. An alternative is to allocate the buffer at system startup, but this would leave the buffer unusable by other processes and would result in a waste of main personal computer memory when the reverberation processor is not being used.
Subsystems which process data in real time typically have a high cost in system resources at the time that data is presented or output required. The bus accesses required to read, store and compute results based on the data occur at the times where data is presented, which in a reverberation processor is the sample interval, or when output is required. When system resources are being used heavily by other processes, there is the possibility of failure. Buffer underrun or overrun can occur, which means the system will not be able to keep up with the real-time processing requirement. Even if failure does not occur, a heavy requirement for system resources at one instant in time can cause a loss of smoothness in other processes, making the graphics display or a human input controller operate irregularly. The present invention distributes the resources required by a reverberation processor by ensuring that only one block transfer for one tap can occur at a single sample interval.
SUMMARY OF THE INVENTION
In accordance with one embodiment of the present invention, it is an object of the present invention to provide a reverberation processor for generating digital reverberation using only the main system memory of a personal computer.
It is another object of the present invention to provide a reverberation processor which does not require that the reverberation memory be contiguous, but can comprise blocks of physical memory at arbitrary locations.
It is still another object of the present invention to provide an improved reverberation processor that has consistent and predictable demand on the system bus in order to avoid buffer faults and to minimize impact on other processes and subsystems.
BRIEF DESCRIPTION OF THE PREFERRED EMBODIMENT
In accordance with one embodiment of the present invention, a reverberation processor comprising a register file and an offset logic element for providing an address to memory on a bus and a data storage element for storing reverberation data is disclosed.
The register file is connected to an offset logic block which allows a programmable offset for individual taps and to transfer data over a block of memory. The data is transferred to and from a data storage element for further processing. In order to stagger block transfers so that only one block transfer can occur during a sample period, the data storage elements are pre-loaded to varying fractions of their capacity. This causes subsequent data requests to be offset in time. This balances the load on the system bus and reduces conflicts when more than one reverberator is operating within a system.
REFERENCES:
patent: 4499539 (1985-02-01), Vosacek
patent: 5058076 (1991-10-01), Kuichi
patent: 5140620 (1992-08-01), Woodward
patent: 5473348 (1995-12-01), Fujimoto
patent: 5668338 (1997-09-01), Hewett et al.
patent: 5896291 (1999-04-01), Hewett et al.
patent: 5918253 (1999-06-01), Kadowaki
patent: 5924112 (1999-07-01), Barber et al.
patent: 5971923 (1999-10-01), Finger
Maung Zarni
Philips Semiconductors Inc.
LandOfFree
Digital reverberation processor and method for generating... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Digital reverberation processor and method for generating..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Digital reverberation processor and method for generating... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2537696