Digital processing phase lock loop for synchronous digital micro

Details Digital processing phase lock loop for synchronous digital micro Digital processing phase lock loop for synchronous digital micro

1997-02-04

1999-11-09

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

327156, 327159, 331 25, H03D 324, H03L 706, H03L 700

Patent

active

059828358

ABSTRACT:
A digital processing phase lock loop for use in a synchronous micro-wave transmitter includes: a reference clock receiving unit for receiving an electric signal or an optical signal of 8 KHz as an reference clock from an external signal input unit or a switching unit; a phase comparator for comparing the reference clock output from the reference clock receiving unit with a self-clock feedback depending on a counter clock of 19.44 MHz and then producing phase detection information of 8 bits; a phase control unit for performing a phase control according to the period of phase control corresponding to a predetermined mode, including at least one of superhigh speed mode, a high speed mode and a low speed mode with inputting the phase detection information and for performing a looppass filtering for jitter suppression, thereby outputting data of 16 bits; a signal converter for converting the data of 16 bits into an analog signal; a VCO(Voltage Controlled Oscillator) for operating by inputting the analog signal according to its instantaneous frequency; and a frequency divider for dividing output frequency of the VCO and then feeding back the divided output frequency, thereby outputting a self-clock of 8 KHz to the phase comparator.

REFERENCES:
patent: 4418318 (1983-11-01), Swagerty et al.
patent: 4752748 (1988-06-01), Grzeszykowski
patent: 4972160 (1990-11-01), Sylvain
patent: 5475325 (1995-12-01), Nezu
patent: 5673004 (1997-09-01), Park
patent: 5717402 (1998-02-01), Chu
patent: 5726607 (1998-03-01), Brede et al.

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