Digital phase locked loop circuit and method therefor

Details Digital phase locked loop circuit and method therefor Digital phase locked loop circuit and method therefor

1998-05-21

2001-01-23

Ghebretinsae, Temesghen (Department: 2734)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C327S147000

Reexamination Certificate

active

06178216

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a digital communication field, and more particularly, to a digital phase locked loop (PLL) circuit having a short initial synchronizing time and a digital PLL method.
2. Description of the Related Art
To connect two different networks, one network must be synchronized with the other. For example, when two different channels, such as a basic channel generally used in a private switching system, and an integrated services digital network (ISDN) which is another network, are connected to each other, data is lost during communication since the channels are not synchronized with each other due to a difference between system clock signals used in each channel.
SUMMARY OF THE INVENTION
To solve the above problem, it is a first objective of the present invention to provide a digital PLL circuit for maintaining two stable systems by correcting a clock signal of one system to synchronize it with a reference clock signal of the other system.
It is a second objective of the present invention to provide a digital PLL circuit which is simple and has a short synchronizing time by synchronizing a clock signal used in a switching system with a reference clock signal of an external network when the service of the external network is received by a private switching system and a keyphone switching system.
It is a third objective of the present invention to provide a digital PLL method for maintaining two stable systems by correcting a clock signal used in one system to synchronize it with a reference clock signal of the other system.
To achieve the first and second objectives, there is provided a digital PLL circuit, comprising an acquisitor for generating a reset signal according to a reference clock signal input from an outside source according to an act mode signal for synchronizing with an external system, a phase detector, reset by the reset signal, for comparing the phase of the reference clock signal with that of a first clock signal self-divided by the same frequency as the reference clock signal, and for generating a phase detection signal, and a frequency synthesizer for generating a corrected clock signal by changing the division ratio of a system clock signal according to the phase detection signal and an act clock signal locked as a final output.
To achieve the third objective, there is provided a digital PLL method, comprising the steps of (a) generating a reset signal according to a reference clock signal input from an outside source according to an act mode signal for synchronizing with an external system, (b) generating a phase detection signal by comparing the phase of the reference clock signal with that of a first clock signal self-divided by the same frequency as that of the reference clock signal, after being reset by the reset signal, and (c) generating a corrected clock signal by changing the division ratio of the system clock signal according to the phase detection signal and generating a locked act clock signal as a final result.


REFERENCES:
patent: 3921095 (1975-11-01), Chu
patent: 5103192 (1992-04-01), Sekine et al.
patent: 5128632 (1992-07-01), Erhart et al.
patent: 5847614 (1998-12-01), Gikbert et al.
patent: 5896066 (1999-04-01), Katayama et al.

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