Digital logic with reduced leakage

Details Digital logic with reduced leakage Digital logic with reduced leakage

2005-12-20

2005-12-20

Chang, Daniel D. (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Signal level or switching threshold stabilization

C327S544000, C365S227000

Reexamination Certificate

active

06977519

ABSTRACT:
A power gate structure and corresponding method are provided for controlling the ground connection of a logic circuit for a plurality of modes, where the power gate structure includes an NFET transistor, a PFET transistor in signal communication with the NFET transistor, source to source and drain to drain, respectively, a ground node in signal communication with the drains of the transistors, and a ground rail in signal communication with the sources of the transistors; and the corresponding method includes decoupling the logic circuit from the ground connection in a first or active mode, holding the logic circuit at about a threshold voltage above the ground connection in a second or state retention mode, and cutting off the current flow between the logic circuit and the ground connection in a third or non-state retentive mode.

REFERENCES:
patent: 5726946 (1998-03-01), Yamagata et al.
patent: 6049245 (2000-04-01), Son et al.

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