Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-01-04
2008-11-18
Trimmings, John P (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C375S371000, C375S354000, C375S357000, C375S355000, C702S079000, C702S069000
Reexamination Certificate
active
07454674
ABSTRACT:
In one embodiment, a jitter detector comprises a logic circuit coupled to receive a plurality of inputs indicative of states captured from a plurality of outputs of a delay chain responsive to a first clock input and a plurality of clocked storage devices coupled to the logic circuit. The logic circuit is configured to identify a first input of the plurality of inputs that is: (i) captured in error from a corresponding one of the plurality of outputs of the delay chain, and (ii) the corresponding one of the plurality of outputs of the delay chain is least delayed by the delay chain among the plurality of outputs that are captured in error. The plurality of clocked storage devices are configured to accumulate an indication of which of the plurality of outputs have been captured in error over a plurality of clock cycles of the first clock input.
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Demas Andrew J.
Hess Greg M.
Jain Ashish R.
Klass Edgardo F.
Merkel Lawrence J.
Meyertons Hood Kivlin Kowert & Goetzel P.C.
P.A. Semi, Inc.
Radosevich Steven D
Trimmings John P
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