Digital event sampling circuit and method

Details Digital event sampling circuit and method Digital event sampling circuit and method

2005-05-03

2005-05-03

DeCady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S738000, C714S819000, C375S354000, C327S156000, C307S409000

Reexamination Certificate

active

06889349

ABSTRACT:
A method and circuit periodically pseudo-randomly select a sample of digital event pulses comprising a logic data signal. A first timer times a first time interval. A second timer times a second time interval within the first time interval. A delay timer, coupled between the first and second timers, pseudo-randomly delays initiation of the second timer from the start of the first time interval. In one embodiment, the first timer is an (N+1)-bit binary counter. The delay timer includes an N-bit round robin latch and seeded by a pseudo-random number generator having fewer than N bits, the round robin latch shifting its contents to form an N-bit pseudo-random number. The second timer is initiated when the value of the first timer is equivalent to the round robin latch. A coincidence circuit passes digital event pulses during the second time interval. A count is accumulated of the sampled digital event pulses.

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