Digital circuit noise margin improvement

Details Digital circuit noise margin improvement Digital circuit noise margin improvement

1996-12-13

1999-06-08

Tokar, Michael

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Input noise margin enhancement

326 27, 326 86, 326 90, H03K 1716

Patent

active

059107308

ABSTRACT:
The present invention provides a circuit for increasing the noise tolerance of a receiving gate. This is accomplished by separating the circuit which sets the positive going threshold, from the circuit which sets the negative going threshold. This eliminates the need of making a design compromise equally suitable to both these threshold requirements. It is achieved by separating the logical drive for switching from a low to a high from the logical drive for switching from a high to a low. Alternate embodiments are presented. In one embodiment, separate drivers for PFET and NFET inverter inputs are employed together with an output latch circuit which prevents the output from being in a floating state. In an alternate embodiment the latch is included in-line with the gate output. An implementation of the invention in a two input AND gate is also described.

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