Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-09-03
2001-11-27
Crane, Sara (Department: 2811)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S253000, C438S396000, C438S627000, C438S650000, C438S686000
Reexamination Certificate
active
06323081
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor devices and the fabrication thereof. More particularly, the present invention pertains to diffusion barrier layers.
BACKGROUND OF THE INVENTION
In the fabrication of integrated circuits, various conductive layers are used. For example, during the formation of semiconductor devices, such as dynamic random access memories (DRAMs), static random access memories (SRAMs), ferroelectric (FE) memories, etc., conductive materials are used in the formation of storage cell capacitors and also may be used in interconnection structures, e.g., conductive layers in contact holes, vias, etc. In many applications, it is preferable that the material used provide effective diffusion barrier characteristics.
For example, effective diffusion barrier characteristics are required for conductive materials used in the formation of storage cell capacitors of memory devices, e.g., DRAMs. As memory devices become more dense, it is necessary to decrease the size of circuit components forming such devices. One way to retain storage capacity of storage cell capacitors of the memory devices and at the same time decrease the memory device size is to increase the dielectric constant of the dielectric layer of the storage cell capacitor. Therefore, high dielectric constant materials are used in such applications interposed between two electrodes. One or more layers of various conductive materials may be used as the electrode material. However, generally, one or more of the layers of the conductive materials used for the electrodes (particularly the lower electrode of a cell capacitor) must have certain barrier properties and oxidation resistance properties. Such properties are particularly required when high dielectric constant materials are used for the dielectric layer of the storage cell capacitor because of the processes used for forming such high dielectric materials, e.g., deposition of high dielectric materials usually occurs at high temperatures (generally greater than about 500° C.) in an oxygen-containing atmosphere.
Generally, various metals and metallic compounds, and typically notable metals such as platinum and conductive oxides such as ruthenium oxide, have been proposed as the electrodes or at least one of the layers of the electrodes for use with high dielectric constant materials. However, reliable electrical connections should generally be constructed which do not diminish the beneficial properties of the high dielectric constant materials. For platinum to function well as a bottom electrode, it must be an effective barrier to the diffusion of oxygen. This is required since any oxidation of underlying silicon upon which the capacitor is formed will result in a decreased series capacitance, thus degrading the storage capacity of the cell capacitor. Platinum, used alone as an electrode layer, is too permeable to oxygen to be used as a bottom electrode of a storage cell capacitor.
Because of the permeability of platinum to oxygen, typically platinum is used as a layer in an electrode stack which acts as the electrode as well as a diffusion barrier for integration of capacitors directly formed on silicon. For example, as described in the article “Novel High Temperature Multilayer Electrode-Barrier Structure for High Density Ferroelectric Memories” by H. D. Bhatt, et al.,
AppL Phys.Letter
, 71(5), Aug. 4, 1997, the electrode barrier structure includes layers of platinum:rhodium alloy, in addition to platinum:rhodium oxide layers, to form electrodes with diffusion barrier properties. Such alloy layers are formed using physical vapor deposition (PVD) processing, e.g., reactive RF sputtering processes.
Many storage cell capacitors are formed using high aspect ratio openings.
For example, in U.S. Pat. No. 5,392,189 to Fazan, et al., entitled “Capacitor Compatible with High Dielectric Constant Materials Having Two Independent Insulative Layers and the Method for Forming Same,” issued Feb. 21, 1995, the storage cell capacitors include a lower electrode that is formed by deposition of a conductive material within a small high aspect ratio opening. Typically, sputtering does not provide a sufficiently conformal layer adequate for formation of an electrode within such a small high aspect ratio opening.
In addition to the formation of capacitor electrodes, the formation of barrier layers for use in other applications, e.g., interconnect applications, is also desirable. For example, diffusion barriers are commonly used to prevent undesirable reactions in contact openings.
SUMMARY OF THE INVENTION
To overcome the problems described above with respect to the use of platinum alone as an electrode material, and others which will be apparent from the detailed description below, a platinum:ruthenium diffusion barrier layer, structures incorporating such layers, and methods associated therewith are described herein.
A method for use in the fabrication of integrated circuits according to the present invention includes providing a substrate assembly having a surface and forming a barrier layer over at least a portion of the surface. The barrier layer is formed of a platinum(x):ruthenium(1−x) alloy, where x is in the range of about 0.60 to about 0.995.
In other embodiments of the method, preferably, x is in the range of about 0.90 to about 0.98, and more preferably, x is about 0.95. In another embodiment of the method, the barrier layer is formed by chemical vapor deposition. In yet another embodiment of the method, the portion of the surface upon which the barrier layer is formed is a silicon containing surface.
Another method for use in the formation of a capacitor according to the present invention includes forming a first electrode on a portion of a substrate assembly. A high dielectric material is formed over at least a portion of the first electrode and a second electrode is formed over the high dielectric material. At least one of the first and second electrodes comprises a layer of a platinum:ruthenium alloy.
In one embodiment of the method, at least one of the first electrode and second electrode includes the layer of platinum(x):ruthenium(1−x) alloy and one or more additional conductive layers.
Another method for use in forming a storage cell including a capacitor according to the present invention is described. The method includes providing a substrate assembly including at least one active device and forming a capacitor relative to the at least one active device. The capacitor comprises at least one electrode including a barrier layer of platinum(x):ruthenium(1−x) alloy.
A semiconductor device structure according to the present invention includes a substrate assembly including a surface and a barrier layer over at least a portion of the surface. The barrier layer is formed of a platinum(x):ruthenium(1−x) alloy, wherein x is in the range of about 0.60 to about 0.995.
A capacitor structure according to the present invention includes a first electrode, a dielectric material on at least a portion of the first electrode, and a second electrode on the dielectric material. At least one of the first and second electrodes comprises a barrier layer of platinum(x):ruthenium(1−x) alloy.
A memory cell structure according to the present invention includes a substrate assembly including at least one active device and a capacitor formed relative to the at least one active device. The capacitor comprises at least one electrode including a barrier layer formed of platinum(x):ruthenium(1−x) alloy.
Another integrated circuit structure includes a substrate assembly including at least one active device and an interconnect formed relative to the at least one active device. The interconnect including a barrier layer formed of platinum(x):ruthenium(1−x) alloy.
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patent: 5
Crane Sara
Micro)n Technology, Inc.
Mueting Raasch & Gebhardt, P.A.
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