Differential sensing and TSV timing control scheme for 3D-IC

Details Differential sensing and TSV timing control scheme for 3D-IC Differential sensing and TSV timing control scheme for 3D-IC

2011-06-28

2011-06-28

Crawford, Jason M (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C326S041000, C326S047000, C257S758000, C257S777000, C716S119000, C716S126000

Reexamination Certificate

active

07969193

ABSTRACT:
This disclosure uses a differential sensing and TSV timing control scheme for 3D-IC, which includes a first chip layer of the stacked device having a detecting circuits and a relative high ability driver horizontally coupled to the detecting circuits. A sensing circuit is coupled to the detecting circuits by a horizontal line, a first differential signal driver is coupled to the sensing circuit, horizontally. The Nth chip layer of the stacked device includes a Nth relative high ability driver and a Nth differential signal driver formed on the Nth chip layer. The Nth relative high ability driver is vertically coupled to the first relative high ability driver through one relative low loading TSV and (N−2) TSVs to act as dummy loadings. The TSV and (N−2) TSVs penetrate the stacked device from Nth chip layer to first chip layer. The TSV shares same configuration with the (N−2) TSVs. The Nth differential signal driver is vertically coupled to the first differential signal driver through a pair of TSVs and (N−2) pairs of TSVs, vertically. The pair of TSVs and the (N−2) TSVs penetrate the stacked device from the Nth chip layer to the first chip layer. Each of TSV is formed between a first and a second chip layers. Each of TSV is formed between any adjacent two chip layers of the stacked device.

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