Differential receiver architecture

Details Differential receiver architecture Differential receiver architecture

2005-02-15

2005-02-15

Dildine, R. Stephen (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S736000

Reexamination Certificate

active

06857089

ABSTRACT:
A receiver circuit for a tester for electronic devices is provided. The receiver circuit includes a clock receiver that is adapted to receive a source synchronous clock signal from a device under test. The receiver circuit further includes a data receiver that is responsive to the clock circuit. The data receiver is adapted to receive at least one differential data signal from the device under test. The receiver circuit also includes a trigger receiver that is responsive to the clock circuit. The trigger receiver is adapted to receive a trigger signal from the device under test. Finally, the receiver circuit includes a control circuit that is coupled to the trigger receiver. The control circuit is adapted to generate a start alignment capture signal based on the received trigger signal to initiate capture of data received at the data receiver for comparison with expected values.

REFERENCES:
patent: 6181616 (2001-01-01), Byrd
patent: 6329831 (2001-12-01), Bui et al.
patent: 6430725 (2002-08-01), Reichle et al.
patent: 6486693 (2002-11-01), Conner et al.
patent: 20030028832 (2003-02-01), Schaber et al.
patent: WO0013186 (2000-03-01), None
Dinh, Van D. et al: “An Approach to Testing 200 ps Echo Clock to Output Timing on the Double Data Rate Synchronous Memory”; Proceedings ITC, 2000; Baltimore MD, Oct. 30-Nov. 1, 2000, pp. 610-618.

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