Static information storage and retrieval – Read/write circuit – Precharge
Patent
1991-08-07
1994-04-19
Sikes, William L.
Static information storage and retrieval
Read/write circuit
Precharge
36518905, 365205, 307530, G11C 700
Patent
active
053052692
ABSTRACT:
A differential latching inverter uses a pair of cross-coupled inverters having a skewed voltage transfer function to rapidly sense a differential signal on a pair of bit lines in a random access memory and provide high speed sensing during a read operation. The differential latching inverter may also include a pair of symmetrical transfer function output inverters and additional pull-up circuits to enhance high speed operation. The differential latching inverter may be used in a memory architecture having primary bit lines and signal bit lines, with a differential latching inverter being connected to each pair of signal bit lines. The primary bit lines and signal bit lines are coupled to one another during read and write operations and decoupled from one another otherwise. The read and write operations may be internally timed without the need for external clock pulses in response to a high speed address change detection system, and internal timing signals generated by delay ring segment buffers. A high speed, low power random access memory may thereby be provided.
REFERENCES:
patent: 4354257 (1982-10-01), Varshney et al.
patent: 4612631 (1986-09-01), Ochii
patent: 4616148 (1986-10-01), Ochii et al.
patent: 4636985 (1987-01-01), Aoki et al.
patent: 4740926 (1988-04-01), Takemae et al.
patent: 4764901 (1988-08-01), Sakurai
patent: 4816706 (1989-03-01), Dhong et al.
patent: 4831287 (1989-05-01), Golab
patent: 4843264 (1989-06-01), Galbraith
patent: 4845381 (1989-07-01), Cuevas
patent: 4845672 (1989-07-01), Watanabe et al.
patent: 4893278 (1990-01-01), Ito
patent: 4899317 (1990-02-01), Hoekstra et al.
patent: 4903238 (1990-02-01), Miyatake et al.
patent: 4984204 (1991-01-01), Sato et al.
IBM Tech. Discl. Bultn., "High-Sensitivity, High-Speed FET Sense Latch", Bishop et al., Sep. 1975, pp. 1021-1022.
IEEE Intl. Solid-State Ckts. Conf., Ochii et al., "High Density SRAMS", pp. 64-65, 1985.
8ns CMOS 64kx4 and 256x1 SRAMs, S. Flannagan et al., 1990 IEEE International Solid-State Circuits Conference, pp. 134-135, 282, 100-101.
Current-Mode Techniques for High-Speed VLSI Circuits with Application to Current Sense Amplifier for CMOS SRAMs, E. Seevinck et al., IEEE Journal of Solid-State Circuits, vol. 26, No. 4, Apr., 1991, pp. 525-535.
Cunningham Terry D.
Sikes William L.
Thunderbird Technologies, Inc.
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