Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent
1998-07-07
2000-04-18
Tu, Trinh L.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
714724, 324763, G06F 1100, G01R 3128
Patent
active
060528109
ABSTRACT:
A tester circuit generating differential signals, single ended signals, or a fast transitioning signal to exercise inputs of a device under test is described. According to one embodiment, the tester circuit includes a first circuit configured to generate a first test signal on an input of the first driver. The tester circuit also includes a second circuit configured to generate a second test signal on an input of a second driver. Further, the tester circuit also includes select signals and select logic to determine the different testing modes of the device under test.
REFERENCES:
patent: 4439858 (1984-03-01), Petersen
patent: 4791358 (1988-12-01), Sauerwald et al.
patent: 5875198 (1999-02-01), Satoh
Gillete, Garry C., A Single Board Test System: Changing the Test Paradigm, IEEE (1995), Paper 37.2, pp. 880-885.
LTX Corporation
Tu Trinh L.
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