Differential CMOS logic family

Details Differential CMOS logic family Differential CMOS logic family

1997-08-19

1999-12-28

Santamauro, Jon

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Field-effect transistor

326 50, 326121, 327408, H03K 190948

Patent

active

06008670&

ABSTRACT:
Disclosed herein is a differential CMOS cell that achieves faster switching speeds than conventional CMOS logic by 1) biasing a differential pair of output nodes to a relatively high logic low voltage threshold, and 2) pulling up the differential pair of output nodes to a logic high voltage level. The differential CMOS cell is designed such that the difference between logic low and logic high voltage thresholds is much less than in traditional CMOS circuits (i.e., approximately 0.8 V-1.0 V as compared to 2.6 V). A lower voltage swing allows for fast switching of a differential output signal. In a preferred embodiment, the differential CMOS cell receives a primary differential input signal, and respective first and second secondary differential input signals. The differential CMOS cell includes a differential pair of arm circuits, each comprising a primary input switch for receiving a component of the primary differential input signal, and a differential pair of secondary input switches for receiving either the first or second secondary differential input signal. Each arm circuit is coupled between a current source and a voltage source. In operation, the primary differential input signal selects one of the first or second secondary differential input signals to be output as the differential output signal.

REFERENCES:
patent: 4686392 (1987-08-01), Lo
patent: 5124588 (1992-06-01), Baltus et al.
patent: 5149992 (1992-09-01), Allstot et al.
patent: 5216295 (1993-06-01), Hoang
patent: 5298810 (1994-03-01), Scott et al.
patent: 5319348 (1994-06-01), Lee et al.
patent: 5583456 (1996-12-01), Kimura
patent: 5625308 (1997-04-01), Matsumoto et al.
patent: 5798658 (1998-08-01), Werking
Serial No. 08/855,976 filed May 14, 1997 Means For Virtual Deskewing of High/Intermediate/Low Dut Data of Barbara J. Duffner, et al.
IEEE Journal Of Solid-State Circuits, vol. 31, No. 4, Apr. 1996, "An Efficient Charge Recovery Logic Circuit", 9 pages, by Yong Moon and Deog-Kyoon Jeong.

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