Differential bit line clamp

Details Differential bit line clamp Differential bit line clamp

1987-01-28

1988-11-15

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365207, 365242, G11C 700, G11C 702, G11C 800

Patent

active

047854278

ABSTRACT:
A semiconductor memory for storing binary data which may be accessed more rapidly is disclosed which semiconductor memory includes a pair of differential bit lines for receiving signals corresponding to the binary data; a semiconductor memory device for storing binary data is coupled between the differential bit lines to provide signals corresponding to the binary data when reading the semiconductor memory device during the read cycle. A semiconductor clamping device is coupled between the differential bit lines to selectively provide a current path between the differential bit lines during the reading of the semiconductor device.

REFERENCES:
patent: 4612631 (1986-09-01), Ochii
patent: 4616344 (1986-10-01), Noguchi et al.
patent: 4627032 (1986-12-01), Kolwicz et al.
patent: 4656608 (1987-04-01), Aoyama
IBM Technical Disclosure Bulletin, Barsuhn et al., "Semiconductor Storage Circuit Utilizing Two Device Memory Cells", vol. 18, No. 3, Aug. 1975.

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