Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2006-11-14
2006-11-14
Wilczewski, Mary (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S261000, C438S288000, C438S770000, C438S785000
Reexamination Certificate
active
07135370
ABSTRACT:
A non-volatile memory (NVM) cell, which uses a storage dielectric as the storage element, has a top dielectric between a gate and the storage dielectric and a bottom dielectric between a semiconductor substrate and the storage dielectric. The top dielectric includes a relatively thick and high k dielectric layer and an interfacial layer. The interfacial layer is very thin and has a higher k than silicon oxide. The bottom dielectric layer is preferably silicon oxide because of its interfacial and tunneling properties. The cell thus has benefits resulting from a well-passivated, high k top dielectric in combination with a bottom dielectric of silicon oxide.
REFERENCES:
patent: 4360900 (1982-11-01), Bate
patent: 5861347 (1999-01-01), Maiti et al.
patent: 5876788 (1999-03-01), Bronner et al.
patent: 6245652 (2001-06-01), Gardner et al.
patent: 6297095 (2001-10-01), Muralidhar et al.
patent: 6511925 (2003-01-01), Aronowitz et al.
patent: 6645882 (2003-11-01), Halliyal et al.
patent: 6812517 (2004-11-01), Baker
patent: 2002/0086548 (2002-07-01), Chang
patent: 2003/0042527 (2003-03-01), Forbes et al.
patent: 2003/0047755 (2003-03-01), Lee et al.
patent: 2003/0049942 (2003-03-01), Haukka et al.
patent: 2003/0153149 (2003-08-01), Dong et al.
patent: 2004/0087079 (2004-05-01), Chen et al.
patent: 2005/0059259 (2005-03-01), O'Meara et al.
patent: 19903598 (2000-08-01), None
patent: WO 8204126 (1982-11-01), None
Patent Abstracts of Japan, vol. 007, No. 099 (E-172). Apr. 27, 1983 and JP 5802871A (Tokyo Shibaura Denki KK), Feb. 8, 1983, abstract, figures.
Lee et al., “A Novel High K Inter-Poly Dielectric (IPD), Al2O3for Low Voltage/High Speed Flash Memories: Erasing in msecs at 3.3V,” 1997 Symposium on VLSI Technology Digest of Technical Papers, Jun. 1997, pp. 117-118.
PCT/US 03/22991 International Search Report.
Clingan, Jr. James L.
Freescale Semiconductor Inc.
King Robert L.
Thomas Toniae M.
Wilczewski Mary
LandOfFree
Dielectric storage memory cell having high permittivity top... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Dielectric storage memory cell having high permittivity top..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dielectric storage memory cell having high permittivity top... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3669394