Dielectric memory cell structure with counter doped channel...

Details Dielectric memory cell structure with counter doped channel... Dielectric memory cell structure with counter doped channel...

2006-12-19

2006-12-19

Le, Thao X. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S315000, C257SE29309

Reexamination Certificate

active

07151292

ABSTRACT:
A charge trapping dielectric memory cell array comprises a plurality of parallel bit lines implanted within the lightly doped substrate. The parallel bit lines define a plurality of channel regions spaced there between and form a semiconductor junction there with. A plurality of parallel and spaced apart word lines are positioned above the surface of the substrate and separated from the substrate by a charge trapping dielectric. The plurality of parallel word lines are perpendicularly positioned with respect to the bit lines. Each channel region comprises a central counter doped channel region adjacent to a top surface of the substrate and vertically extending into the channel region to a depth less than the bit line depth and being spaced from each semiconductor junction by a pocket region.

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