Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2003-06-11
2004-09-07
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S240000, C438S957000
Reexamination Certificate
active
06787412
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a dielectric element having a lower electrode, a dielectric layer, and an upper electrode in which Pt is used as an electrode material, and a method for fabricating such a dielectric element.
2. Description of Relevant Art
In recent years, attempts have been made actively to apply a dielectric element fabricated by using a high dielectric material such as BTO, STO or BST, or by using a ferroelectric material such as SBT, SBTN or PZT to a next-generation highly integrated DRAM or non-volatile memory.
Each of the aforementioned dielectric materials is made of plural metal oxides. Since a process for forming a dielectric layer is performed in an oxidative atmosphere, it is desirable to use a conductive material as an electrode material for a dielectric element that is not likely to be oxidized, or exhibits a conductivity even when it is oxidized.
Those conductive materials include metals such as Pt, Ir, Ru, Rh, Re, Os, and Au, and oxides thereof. Above all, a dielectric element using Pt as an electrode material has been attracting attention due to the excellent conductivity, the heat and chemical stability, the ability to form a high dielectric thin film or a ferroelectric thin film with a desirable orientation controllability, etc.
In order to increase the degree of integration of IC circuits, it will be desired in the future to micro-process dielectric elements on the order of about 0.5 &mgr;m or less, particularly about 0.2 &mgr;m or less. However, the mass-production processing limit, i. e., etching performance, of a Pt electrode is about 0.8 &mgr;m at present, and the electrode after the processing is likely to have a tapered or trapezoidal shape. Thus, an increase in the degree of integration of IC circuits using Pt still has problems to be solved.
Moreover, since it is difficult to perform etching Pt by a chemical reaction with a halogen gas, Pt is generally processed physically by a sputtering method and the like. However, the damage caused to a dielectric layer during such a physical processing method deteriorates electrical characteristics of the dielectric element.
Furthermore, it takes a long time to process Pt, and Pt residues generated during the processing may be adhered to an inner wall of a processing chamber, thereby causing contamination. Therefore, it is necessary to clean the inside of the processing chamber and an etcher every time when the processing is completed of several wafers.
Reports on Pt electrode materials in dielectric elements have been made in various articles. “Monthly Semiconductor World” (November, 1998, pp. 62-67) discloses a semiconductor element where BST, a high dielectric material, is used as a dielectric layer, and Pt is used as an electrode material. It also describes that as Pt is mostly processed by physical sputtering method, an etched-away residue or product may be adhered to the processed Pt electrode surface, or a Pt electrode may have a tapered shape, thereby making it difficult to form a fine pattern.
“Monthly Semiconductor World” (July, 1999, pp. 30-34) teaches a method of forming Pt lower electrode in a contact hole on a substrate by electroplating, where an Ru layer is provided as an electroplating seed layer onto an entire inner surface of the contact hole, and an SiO
2
film is used as a plating mask layer, in the fabrication of a dielectric element having a self-aligned stacked (SAS) capacitor structure using BST, a high dielectric material, as a dielectric layer.
In such a case, however, the Pt plated layer grows not only from the Ru layer on the bottom surface of the contact hole, but also from the Ru layer on the inner side surface of the contact hole. Therefore, a coarse plated layer having voids or seams may be resulted.
Furthermore, the SiO
2
film used as the plating mask should be dry-etched and removed by using a strong acid fluorine-based gas such as CF
4
, CHF
3
, or C
2
F
6
. Therefore, during the etching process, an insulating film, generally an SiO
2
layer, on the substrate will also be stripped away.
In order to avoid such a problem, a wet etching or removing method using an HF solution may be used. However, the removal effect thereof is smaller than that of by the dry etching method, and the wet etching method has the problem of a particle generation. Also, the Ru seed layer cannot be removed by the HF solution. Therefore, after the SiO
2
film as a mask is removed by the HF solution, the Ru seed layer needs to be separately removed by dry etching. Thus, the wet etching method has a poor production efficiency.
Unexamined Published Japanese Patent Application (Kokai) No. 335588/1998 discloses a method for fabricating a ferroelectric element having a structure where a ferroelectric substance is interposed between electrodes containing a noble metal as its main component, wherein a base layer such as Pd, Ni, Ti, or TiN that catalyzes the plating of the noble metal is firstly formed, and then the noble metal is deposited onto the base layer by a plating method to form an electrode. However, it has problems that each of the afore-mentioned materials for the base layer loses its conductivity when oxidized by a heat treatment in the oxygen atmosphere, thereby deteriorating the conductivity of the electrode. Moreover, it is difficult to remove the base layer made of each of the said materials by etching, and the material etched away may contaminate the inside of the processing chamber.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a dielectric element using Pt as an electrode material, that is capable of easily forming a Pt electrode having excellent electrical characteristics without generating voids or seams, that is capable of forming a fine pattern, and that does not occur contamination in a processing chamber.
Another object of the present invention is to provide a method for fabricating a dielectric element of having the characteristics mentioned above.
As a result of intensive studies made in order to solve the above-described problems, the present inventors found out that, in the formation of a Pt electrode by electroplating, the prior art problem occurred by the use of said strong acid material for removing a mask can be solved by using a photoresist layer instead of the SiO
2
layer as a mask for electroplating, that is capable of being removed by an oxygen plasma treatment.
Moreover, the present inventors found out that the prior art problem of contamination occurred in the processing chamber during the removal of the seed layer can be solved by using an Ru material, as a seed layer for forming a Pt plated layer, whose oxide exhibits a conductivity and can be easily removed by an oxygen plasma treatment.
Furthermore, the present inventors found out that the prior art problem caused by using an SiO
2
film as a mask, and by forming an Ru layer on an entire inner surface of a contact hole as a seed layer, can be solved by forming a photoresist pattern onto an Ru layer over a substrate as a plating mask, and by performing Pt electroplating onto an exposed area of the Ru layer where no mask pattern is formed.
Thus, the present invention provides a dielectric element formed by sequentially depositing on a substrate an Ru layer, a Pt layer, a dielectric layer which is a ferroelectric layer, and a Pt layer (hereinafter, referred to as a “first dielectric element”).
The present invention also provides a method for fabricating a dielectric element (hereinafter, referred to as a “first dielectric element fabrication method”) which comprises:
(I) forming an Ru layer on a substrate;
(II) forming a photoresist layer on the Ru layer;
(III) selectively exposing the photoresist layer, and forming a photoresist pattern as a mask on the Ru layer;
(IV) forming a Pt layer, which is to be a lower electrode, on an exposed or unmasked area of the Ru layer by electroplating using a Pt plating solution utilizing the Ru layer as an electroplating electrode;
(V) removing the photoresist pattern and the Ru layer pro
Hashimoto Akira
Kawakami Atsushi
Kobari Hideya
Nakajima Tetsuya
Sato Yoshimi
Fourson George
Pham Thanh V
Tokyo Ohka Kogyo Co. Ltd.
Wenderoth,Lind&Ponack, LLP
LandOfFree
Dielectric element and method for fabricating the same does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Dielectric element and method for fabricating the same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dielectric element and method for fabricating the same will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3213937