Die with integral pedestal having insulated walls

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Chip mounted on chip

Reexamination Certificate

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Details

C257S685000, C257S723000, C257SE23085, C257SE25005, C257SE25006, C257SE23021, C257SE23023, C438S109000

Reexamination Certificate

active

07067927

ABSTRACT:
A variety of techniques and structures are described that integrate an insulated pedestal into the back surface of integrated circuit dice. The die has an insulated integral pedestal formed therein that acts as a spacer. The pedestal has a footprint that is smaller than the total footprint of the die so that a portion of the active region of the die overhangs the pedestal. The geometry of the pedestal may be widely varied and in some embodiments, multiple pedestals may be provided on the stacked die. In another aspect, the pedestals are formed at the wafer level such that the pedestals are defined in the back surface of the wafer. Often, the thickness of the pedestals will be thicker than the portions of the wafer outside the pedestal areas. The described dice are particularly well suited for use in stacked die packages.

REFERENCES:
patent: 6023094 (2000-02-01), Kao et al.
patent: 6075290 (2000-06-01), Schaefer et al.
patent: 6175162 (2001-01-01), Kao et al.
patent: 6548323 (2003-04-01), Perry et al.
patent: 6777797 (2004-08-01), Egawa
patent: 6911723 (2005-06-01), Akram
patent: 2004/0245652 (2004-12-01), Ogata
U.S. Appl. No. 10/969,729, filed Oct. 19, 2004.

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