Semiconductor device manufacturing: process – Bonding of plural semiconductor substrates – Having enclosed cavity
Reexamination Certificate
2001-08-02
2002-04-30
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Bonding of plural semiconductor substrates
Having enclosed cavity
C257S668000
Reexamination Certificate
active
06380048
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and, more particularly, to a method and package for packaging semiconductor die in such a manner that die-paddle surface delamination is prevented.
(2) Description of the Prior Art
The semiconductor industry has for many years achieved improvements in the performance of semiconductor devices by device miniaturization and by increasing the device packaging density. For this purpose, metal interconnects can readily be provided by metal lines that are embedded in layers of dielectric, using vias to provide electrical connections between overlying layers of interconnect lines. Interconnect lines must thereby be connected in such a manner that optimum performance can be realized for the completed package. Good planarity must also be maintained between adjacent layers of interconnect lines because metal interconnect lines are typically narrow in width and thick in a vertical direction (in the range of 5 to 10 microns thick) and must be patterned with microlithography. Patterned layers must therefore be substantially flat and smooth (i.e. have good planarity) so that these layers can serve as a base for the next layer.
One of the original approaches that has been used to create surface mounted, high pin-count integrated circuit packages has been the use of the Quad Flat Pack (QFP) with various pin configurations. For the QFP, closely spaced leads along the four edges of the flat package are used for making electrical connections from where the electrical connections are distributed to the surrounding circuitry. The QFP has found to be cost-effective for semiconductor devices where the device I/O pin count does not exceed 200. To circumvent this limitation, a new package, a Ball Grid Array (BGA) package has been introduced. For the BGA package, the electrical contact points are distributed over the entire bottom surface of the package. More contact points with greater spacing between the contact points can therefore be allocated across the BGA package than was the case with the QFP.
Flip Chip packages have in general been used to accommodate increased I/O count combined with increased high requirements for high performance Integrated Circuits. Flip chip technology fabricates bumps (typically Pb/Sn solder) on aluminum pads and interconnects the bumps directly to the packaging media, which are usually ceramic or plastic based substrates. The flip-chip is bonded face down to the package through the shortest paths. This approach can be applied to single-chip packaging and to higher levels of integrated packaging (in which the packages are larger) and to more sophisticated packaging media that accommodate several chips to form larger functional units.
For the packaging of semiconductor devices, the packages in which the devices are contained provide protection of the device from environmental influences such as mechanical damage or damage caused by moisture affecting exposed surfaces of the device. Part of the package design includes the design of electrically conductive interfaces that enable the device to be electrically interconnected with surrounding circuitry. Increased device density has not only created new demands for input/output connections of the device but has also caused considerable more thermal energy to be expanded per cubic volume content of the device. In many of the semiconductor device packages, the device is mounted in close physical proximity to a heat sink. This is combined with methods, such as connections of low resistance to thermal heat conductivity, that are implemented as part of the package.
U.S. Pat. No. 5,977,626 (Wang et al.) shows an enhanced PBGA package with a ground ring and die-paddle.
U.S. Pat. No. 5,1814,877 (Diffenderfer et al.), U.S. Pat. No. 5,639,694 (Diffenderfer et al.), U.S. Pat. No. 5,543,657 (Diffenderfer et al.) show packages with ground ring and die-paddle configurations.
U.S. Pat. No. 5,942,794 (Okumura et al.) provides for a plastic encapsulated semiconductor device package using related technologies.
U.S. patent application Ser. No. 09/395,923, filed on Sep. 14, 1999, Titled “Leadframe Based Chip Scale Package and Method of Producing the Same”, assigned to a common assignee.
SUMMARY OF THE INVENTION
A principle objective of the invention is to provide a method and package of an enhanced die-paddle design.
Another objective of the invention is to provide a leadframe of reduced internal stress for the mounting of semiconductor devices.
Yet another objective of the invention is to provide a leadframe of an improved interlocking design for the mounting of semiconductor devices.
A still further objective of the invention is to provide a leadframe for the mounting of semiconductor devices that provides the required shielding of the package against drastic environmental changes.
In accordance with the objectives of the invention a new design is provided for the die-paddle that is used as part of a package for packaging semiconductor devices. The new design of the invention creates a space between the ground ring of the die-paddle and the surface over which the ground-paddle is mounted. The new design further comprises an S-shaped segment between the ground-ring and the center of the die-paddle, the S-shaped segment provides stress relieve between the ground-ring and the center of the die-paddle.
REFERENCES:
patent: 5543657 (1996-08-01), Diffenderfer et al.
patent: 5639694 (1997-06-01), Diffenderfer et al.
patent: 5814877 (1998-09-01), Diffenderfer et al.
patent: 5942794 (1999-08-01), Okumura et al.
patent: 5977626 (1999-11-01), Wang et al.
patent: 6331451 (2001-12-01), Fusaro et al.
U.S. Patent Application Ser. No. 09/395,923 filed on Sep. 14, 1999, Titled “Leadframe Based Chip Scale Package and Method of Producing the Same”, assigned to a common assignee.
Boon Tan Hien
Trasporto Arnel
Zheng Zheng
Ackerman Stephen B.
Nelms David
Saile George O.
St Assembly Test Services Pte Ltd
Vu David
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