Die level integrated interconnect decal manufacturing method...

Details Die level integrated interconnect decal manufacturing method... Die level integrated interconnect decal manufacturing method...

2010-03-25

2011-11-08

Sarkar, Asok (Department: 2891)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Including adhesive bonding step

C257SE21503, C257SE21508, C438S108000

Reexamination Certificate

active

08053283

ABSTRACT:
A die level integrated interconnect decal manufacturing method and apparatus for implementing the method. In accordance with the technology concerning the soldering of integrated circuits and substrates, and particularly providing for solder decal methods forming and utilization, in the present instance there are employed underfills which consist of a solid film material and which are applied between a semiconductor chip and the substrate in order to enhance the reliability of a flip chip package. In particular, the underfill material increases the resistance to fatigue of controlled collapse chip connect (C4) bumps.

REFERENCES:
patent: 5128746 (1992-07-01), Pennisi et al.
patent: 5673846 (1997-10-01), Gruber
patent: 6746896 (2004-06-01), Shi et al.

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