Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-05-22
2007-05-22
Kerveros, James C. (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
10825409
ABSTRACT:
A test apparatus including a means for sending a first test pattern to a device under test (DUT), where the first test pattern is a part of a planned sequence of tests, and further including a means for evaluating the test results received from the DUT, and a method of testing are described. The test results may include anomalous data indicative of a defect in the DUT. If so, a second test pattern that is not part of the planned sequence of tests is selected. The second test pattern is selected based on a diagnosis of the anomalous data by the test apparatus.
REFERENCES:
patent: 5646948 (1997-07-01), Kobayashi et al.
patent: 6950974 (2005-09-01), Wohl et al.
Garcia Rodolfo E.
West Burnell G.
Credence Systems Corporation
Kerveros James C.
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